Sebastien Bourdeauducq 74cf074538 drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times		2017-06-21 17:01:52 +08:00
..
amp	firmware: don't build libdyld through misoc.	2017-03-14 08:33:31 +00:00
drtio	drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times	2017-06-21 17:01:52 +08:00
dsp	sawg: register pre-hbf adder	2017-06-13 18:15:44 +02:00
rtio	rtio: refactor RelaxedAsyncResetSynchronizer	2017-06-18 14:37:08 +02:00
targets	drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times	2017-06-21 17:01:52 +08:00
test	test_sawg_fe: add ref_multiplier to simulated core	2017-06-16 19:45:24 +02:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9_dds.py	ad9xxx -> ad9_dds	2017-01-04 11:34:52 +01:00
ad9154_fmc_ebz.py	Merge remote-tracking branch 'm-labs/phaser2' into phaser2	2016-12-02 14:11:56 +01:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
spi.py	spi: fix xfers with full data_width (closes #615)	2017-01-03 19:51:14 +01:00