David Nadlinger bc3b55b1a8 gateware/eem: Force IOB=TRUE on Urukul SYNC output ... Without this, the final register in the SYNC signal TTLClockGen isn't (always) placed in the I/O tile, leading to more jitter than necessary, and causing "double window" artefacts. See sinara-hw/Urukul#16 for more details. (Patch based on work by Weida Zhang, testing by various members of the community in Oxford and elsewhere.)		2019-11-05 17:14:07 +08:00
..
amp	refactor targets	2018-01-22 18:25:10 +08:00
drtio	rtio: use BlindTransfer from Migen	2019-07-05 18:46:18 +08:00
dsp	sawg: don't use Cat() for signed signals	2018-06-09 07:33:47 +00:00
grabber	grabber: fix frame size off-by-1	2018-09-07 16:55:43 +02:00
rtio	rtio/ttl: expose OE	2019-10-16 18:48:20 +08:00
suservo	gateware/suservo: Avoid magic number for activation delay width	2019-06-14 23:45:40 +01:00
targets	sayma_amc: use all transceivers on master (#1230)	2019-11-02 12:12:32 +08:00
test	remove serwb	2019-10-06 18:10:23 +08:00
wrpll	wrpll: add I2CMasterMachine	2019-08-27 18:02:05 +08:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9_dds.py	ad9xxx -> ad9_dds	2017-01-04 11:34:52 +01:00
eem.py	gateware/eem: Force IOB=TRUE on Urukul SYNC output	2019-11-05 17:14:07 +08:00
fmcdio_vhdci_eem.py	fmcdio_vhdci_eem: commit missing part of previous commit	2018-07-17 20:30:13 +08:00
jesd204_tools.py	jesd204: remove ibuf_disable	2019-10-06 22:26:31 +08:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00