Sebastien Bourdeauducq 4946a53456 Revert "targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance" ... This reverts commit 04b0db1a91.		2016-02-22 17:52:40 +08:00
..
amp	Implement core device storage (fixes #219).	2016-01-10 13:04:55 +00:00
rtio	analyzer: move common to artiq.protocols	2016-01-29 20:26:48 -07:00
targets	Revert "targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance"	2016-02-22 17:52:40 +08:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9xxx.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_clock.py	add information about CLOCK hardware	2016-01-20 21:06:02 -05:00
nist_qc1.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_qc2.py	gateware: clean up and integrate QC2 modifications from Daniel	2016-01-20 21:17:19 -05:00
soc.py	gateware/soc: use new SDRAM API call	2015-12-16 14:59:35 +08:00