forked from M-Labs/artiq
270 lines
10 KiB
Python
Executable File
270 lines
10 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.genlib.io import DifferentialInput
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from jesd204b.common import (JESD204BTransportSettings,
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JESD204BPhysicalSettings,
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JESD204BSettings)
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from jesd204b.phy.gtx import GTXQuadPLL
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from jesd204b.phy import JESD204BPhyTX
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from jesd204b.core import JESD204BCoreTX
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from jesd204b.core import JESD204BCoreTXControl
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores import spi as spi_csr
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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sawg)
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from artiq import __version__ as artiq_version
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class _PhaserCRG(Module, AutoCSR):
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def __init__(self, platform, refclk):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 20/3)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
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p_CLKIN1_PERIOD=20/3, p_CLKIN2_PERIOD=20/3,
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i_CLKIN1=refclk, i_CLKIN2=external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1.2GHz when using 150MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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self.cd_rtio.clk.attr.add("keep")
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platform.add_period_constraint(self.cd_rtio.clk, 20/3)
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class AD9154JESD(Module, AutoCSR):
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def __init__(self, platform):
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self.jreset = CSRStorage(reset=1)
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self.jsync = CSRStatus()
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ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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linerate = 6e9
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refclk_freq = 150e6
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fabric_freq = 150*1000*1000
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refclk = Signal()
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self.clock_domains.cd_jesd = ClockDomain()
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refclk_pads = platform.request("ad9154_refclk")
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self.specials += [
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Instance("IBUFDS_GTE2", i_CEB=0,
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i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=refclk),
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Instance("BUFG", i_I=refclk, o_O=self.cd_jesd.clk),
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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]
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self.cd_jesd.clk.attr.add("keep")
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platform.add_period_constraint(self.cd_jesd.clk, 1e9/refclk_freq)
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qpll = GTXQuadPLL(refclk, refclk_freq, linerate)
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self.submodules += qpll
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self.phys = []
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for i in range(4):
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phy = JESD204BPhyTX(
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qpll, platform.request("ad9154_jesd", i), fabric_freq)
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phy.gtx.cd_tx.clk.attr.add("keep")
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platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
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platform.add_false_path_constraints(self.cd_jesd.clk,
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phy.gtx.cd_tx.clk)
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self.phys.append(phy)
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to_jesd = ClockDomainsRenamer("jesd")
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self.submodules.core = to_jesd(JESD204BCoreTX(self.phys, settings,
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converter_data_width=32))
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self.submodules.control = to_jesd(JESD204BCoreTXControl(self.core))
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sync_pads = platform.request("ad9154_sync")
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jsync = Signal()
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self.specials += [
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DifferentialInput(sync_pads.p, sync_pads.n, jsync),
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MultiReg(jsync, self.jsync.status)
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]
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self.comb += [
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platform.request("ad9154_txen", 0).eq(1),
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platform.request("ad9154_txen", 1).eq(1),
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self.core.start.eq(jsync),
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platform.request("user_led", 3).eq(jsync),
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]
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# blinking leds for transceiver reset status
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for i in range(4):
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counter = Signal(max=fabric_freq)
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self.comb += platform.request("user_led", 4 + i).eq(counter[-1])
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sync = getattr(self.sync, "phy{}_tx".format(i))
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sync += [
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counter.eq(counter - 1),
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If(counter == 0,
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counter.eq(fabric_freq - 1)
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)
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]
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class AD9154(Module, AutoCSR):
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def __init__(self, platform):
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self.submodules.jesd = AD9154JESD(platform)
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self.sawgs = [sawg.Channel(width=16, parallelism=2) for i in range(4)]
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self.submodules += self.sawgs
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for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
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self.sync.jesd += conv.eq(Cat(ch.o))
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class Phaser(MiniSoC, AMPSoC):
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mem_map = {
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"rtio": 0x20000000,
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# "rtio_dma": 0x30000000,
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"mailbox": 0x70000000,
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"ad9154": 0x50000000,
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, cpu_type="or1k", **kwargs):
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MiniSoC.__init__(self,
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cpu_type=cpu_type,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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AMPSoC.__init__(self)
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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platform = self.platform
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platform.add_extension(ad9154_fmc_ebz)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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platform.request("user_led", 1)))
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self.csr_devices.append("leds")
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i2c = platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
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self.csr_devices.append("converter_spi")
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self.config["CONVERTER_SPI_DAC_CS"] = 0
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self.config["CONVERTER_SPI_CLK_CS"] = 1
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self.config["HAS_AD9516"] = None
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self.submodules.ad9154 = AD9154(platform)
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self.csr_devices.append("ad9154")
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rtio_channels = []
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phy = ttl_serdes_7series.Inout_8X(
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platform.request("user_sma_gpio_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sysref_pads = platform.request("ad9154_sysref")
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phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154.sawgs
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for phy in sawg.phys)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.submodules.rtio_crg = _PhaserCRG(
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platform, self.ad9154.jesd.cd_jesd.clk)
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self.csr_devices.append("rtio_crg")
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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# self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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self.register_kernel_cpu_csrdevice("rtio")
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# self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri], # , self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(
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self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.rtio_crg.cd_rtio.clk)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.ad9154.jesd.cd_jesd.clk)
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for phy in self.ad9154.jesd.phys:
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, phy.gtx.cd_tx.clk)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder / KC705 phaser demo")
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builder_args(parser)
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soc_kc705_args(parser)
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args = parser.parse_args()
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soc = Phaser(**soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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