forked from M-Labs/artiq
294 lines
8.6 KiB
Python
294 lines
8.6 KiB
Python
from artiq.language.core import *
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from artiq.language.types import *
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from artiq.coredevice.rtio import rtio_output, rtio_input_timestamp
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class TTLOut:
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"""RTIO TTL output driver.
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This should be used with output-only channels.
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:param channel: channel number
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"""
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.channel = channel
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# in RTIO cycles
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self.o_previous_timestamp = int(0, width=64)
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@kernel
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def output(self):
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pass
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@kernel
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def set_o(self, o):
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rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
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self.o_previous_timestamp = now_mu()
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@kernel
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def sync(self):
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"""Busy-wait until all programmed level switches have been
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effected."""
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while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
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pass
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@kernel
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def on(self):
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"""Sets the output to a logic high state."""
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self.set_o(True)
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@kernel
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def off(self):
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"""Set the output to a logic low state."""
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self.set_o(False)
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@kernel
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def pulse_mu(self, duration):
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"""Pulse the output high for the specified duration
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(in machine units)."""
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self.on()
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delay_mu(duration)
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self.off()
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@kernel
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def pulse(self, duration):
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"""Pulse the output high for the specified duration
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(in seconds)."""
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self.on()
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delay(duration)
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self.off()
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class TTLInOut:
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"""RTIO TTL input/output driver.
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In output mode, provides functions to set the logic level on the signal.
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In input mode, provides functions to analyze the incoming signal, with
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real-time gating to prevent overflows.
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RTIO TTLs supports zero-length transition suppression. For example, if
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two pulses are emitted back-to-back with no delay between them, they will
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be merged into a single pulse with a duration equal to the sum of the
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durations of the original pulses.
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This should be used with bidirectional channels.
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Note that the channel is in input mode by default. If you need to drive a
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signal, you must call ``output``. If the channel is in output mode most of
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the time in your setup, it is a good idea to call ``output`` in the
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startup kernel.
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:param channel: channel number
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"""
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.channel = channel
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# in RTIO cycles
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self.o_previous_timestamp = int(0, width=64)
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self.i_previous_timestamp = int(0, width=64)
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@kernel
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def set_oe(self, oe):
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rtio_output(now_mu(), self.channel, 1, 1 if oe else 0)
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@kernel
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def output(self):
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"""Set the direction to output.
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There must be a delay of at least one RTIO clock cycle before any
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other command can be issued."""
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self.set_oe(True)
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@kernel
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def input(self):
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"""Set the direction to input.
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There must be a delay of at least one RTIO clock cycle before any
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other command can be issued."""
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self.set_oe(False)
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@kernel
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def set_o(self, o):
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rtio_output(now_mu(), self.channel, 0, 1 if o else 0)
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self.o_previous_timestamp = now_mu()
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@kernel
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def sync(self):
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"""Busy-wait until all programmed level switches have been
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effected."""
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while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
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pass
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@kernel
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def on(self):
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"""Set the output to a logic high state.
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The channel must be in output mode."""
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self.set_o(True)
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@kernel
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def off(self):
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"""Set the output to a logic low state.
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The channel must be in output mode."""
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self.set_o(False)
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@kernel
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def pulse_mu(self, duration):
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"""Pulses the output high for the specified duration
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(in machine units)."""
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self.on()
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delay_mu(duration)
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self.off()
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@kernel
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def pulse(self, duration):
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"""Pulses the output high for the specified duration
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(in seconds)."""
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self.on()
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delay(duration)
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self.off()
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@kernel
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def _set_sensitivity(self, value):
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rtio_output(now_mu(), self.channel, 2, value)
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self.i_previous_timestamp = now_mu()
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@kernel
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def gate_rising_mu(self, duration):
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"""Register rising edge events for the specified duration
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(in machine units)."""
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self._set_sensitivity(1)
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delay_mu(duration)
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self._set_sensitivity(0)
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@kernel
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def gate_falling_mu(self, duration):
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"""Register falling edge events for the specified duration
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(in machine units)."""
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self._set_sensitivity(2)
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delay_mu(duration)
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self._set_sensitivity(0)
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@kernel
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def gate_both_mu(self, duration):
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"""Register both rising and falling edge events for the specified
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duration (in machine units)."""
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self._set_sensitivity(3)
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delay_mu(duration)
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self._set_sensitivity(0)
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@kernel
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def gate_rising(self, duration):
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"""Register rising edge events for the specified duration
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(in seconds)."""
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self._set_sensitivity(1)
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delay(duration)
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self._set_sensitivity(0)
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@kernel
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def gate_falling(self, duration):
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"""Register falling edge events for the specified duration
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(in seconds)."""
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self._set_sensitivity(2)
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delay(duration)
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self._set_sensitivity(0)
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@kernel
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def gate_both(self, duration):
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"""Register both rising and falling edge events for the specified
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duration (in seconds)."""
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self._set_sensitivity(3)
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delay(duration)
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self._set_sensitivity(0)
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@kernel
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def count(self):
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"""Poll the RTIO input during all the previously programmed gate
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openings, and returns the number of registered events."""
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count = 0
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while rtio_input_timestamp(self.i_previous_timestamp, self.channel) >= 0:
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count += 1
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return count
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@kernel
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def timestamp_mu(self):
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"""Poll the RTIO input and returns an event timestamp (in machine
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units), according to the gating.
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If the gate is permanently closed, returns a negative value.
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"""
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return rtio_input_timestamp(self.i_previous_timestamp, self.channel)
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class TTLClockGen:
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"""RTIO TTL clock generator driver.
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This should be used with TTL channels that have a clock generator
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built into the gateware (not compatible with regular TTL channels).
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:param channel: channel number
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"""
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def __init__(self, dmgr, channel, core_device="core"):
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self.core = dmgr.get(core_device)
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self.channel = channel
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# in RTIO cycles
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self.previous_timestamp = int(0, width=64)
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self.acc_width = int(24, width=64)
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@portable
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def frequency_to_ftw(self, frequency):
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"""Returns the frequency tuning word corresponding to the given
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frequency.
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"""
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return round(2**self.acc_width*frequency*self.core.coarse_ref_period)
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@portable
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def ftw_to_frequency(self, ftw):
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"""Returns the frequency corresponding to the given frequency tuning
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word.
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"""
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return ftw/self.core.coarse_ref_period/2**self.acc_width
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@kernel
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def set_mu(self, frequency):
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"""Set the frequency of the clock, in machine units.
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This also sets the phase, as the time of the first generated rising
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edge corresponds to the time of the call.
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The clock generator contains a 24-bit phase accumulator operating on
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the RTIO clock. At each RTIO clock tick, the frequency tuning word is
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added to the phase accumulator. The most significant bit of the phase
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accumulator is connected to the TTL line. Setting the frequency tuning
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word has the additional effect of setting the phase accumulator to
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0x800000.
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Due to the way the clock generator operates, frequency tuning words
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that are not powers of two cause jitter of one RTIO clock cycle at the
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output.
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"""
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rtio_output(now_mu(), self.channel, 0, frequency)
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self.previous_timestamp = now_mu()
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@kernel
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def set(self, frequency):
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"""Like ``set_mu``, but using Hz."""
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self.set_mu(self.frequency_to_ftw(frequency))
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@kernel
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def stop(self):
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"""Stop the toggling of the clock and set the output level to 0."""
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self.set_mu(0)
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@kernel
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def sync(self):
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"""Busy-wait until all programmed frequency switches and stops have
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been effected."""
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while self.core.get_rtio_counter_mu() < self.o_previous_timestamp:
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pass
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