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artiq/artiq/gateware
Robert Jördens 32d538f72b kasli: add PTB2 (external clock and SYNC)
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:16 +01:00
..
amp refactor targets 2018-01-22 18:25:10 +08:00
drtio drtio: fix satellite i_status handling 2018-09-19 20:57:21 +08:00
dsp sawg: don't use Cat() for signed signals 2018-06-09 07:33:47 +00:00
grabber grabber: fix frame size off-by-1 2018-09-07 16:55:43 +02:00
rtio use FutureWarning instead of DeprecationWarning 2018-10-21 12:14:51 +08:00
serwb serwb: support single-ended signals 2018-06-13 21:28:21 +08:00
suservo suservo: fix doc typo 2018-09-03 11:48:40 +02:00
targets kasli: add PTB2 (external clock and SYNC) 2018-11-05 19:37:16 +01:00
test sawg: accurate unittest rtio freq 2018-06-08 17:22:13 +02:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
eem.py urukul: add sync_in to eem0-7 name 2018-11-05 19:36:32 +01:00
fmcdio_vhdci_eem.py fmcdio_vhdci_eem: commit missing part of previous commit 2018-07-17 20:30:13 +08:00
jesd204_tools.py jesd204: update core to v0.10 2018-08-17 22:50:07 +08:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
remote_csr.py remote_csr: add sanity check of CSR CSV type column 2018-02-13 20:02:51 +08:00