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artiq/artiq/gateware
Peter Drmota ee0eb238d5 gateware.test.suservo: Fix tests for python >=3.7
Closes #1748
2022-01-11 17:19:13 +08:00
..
amp refactor targets 2018-01-22 18:25:10 +08:00
drtio rtio: use BlindTransfer from Migen 2019-07-05 18:46:18 +08:00
dsp sawg: don't use Cat() for signed signals 2018-06-09 07:33:47 +00:00
grabber grabber: fix frame size off-by-1 2018-09-07 16:55:43 +02:00
rtio sayma: RF switch control is active-low on Basemod, invert 2020-01-16 09:33:16 +08:00
suservo gateware/suservo: Avoid magic number for activation delay width 2019-06-14 23:45:40 +01:00
targets sayma: add comments about CPLL line rate on KU GTH 2020-12-19 17:05:50 +08:00
test gateware.test.suservo: Fix tests for python >=3.7 2022-01-11 17:19:13 +08:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
eem.py gateware/eem: Force IOB=TRUE on Urukul SYNC output 2019-11-05 17:14:07 +08:00
fmcdio_vhdci_eem.py fmcdio_vhdci_eem: commit missing part of previous commit 2018-07-17 20:30:13 +08:00
jesd204_tools.py jesd204_tools: use new syntax from jesd204b core 2020-12-19 17:05:45 +08:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00