|
phy
|
rtio: Inout → InOut
|
2017-03-14 14:18:55 +08:00 |
|
__init__.py
|
rtio: export DMA and CRIInterconnectShared
|
2016-12-01 16:30:29 +08:00 |
|
analyzer.py
|
rtio: handle input timeout in gateware
|
2017-03-03 17:37:47 +08:00 |
|
cdc.py
|
adapt to migen/misoc changes
|
2016-10-31 00:53:01 +08:00 |
|
core.py
|
rtio: handle input timeout in gateware
|
2017-03-03 17:37:47 +08:00 |
|
cri.py
|
drtio: input support (untested)
|
2017-03-13 23:54:44 +08:00 |
|
dma.py
|
gateware: reverse bytes of SDRAM word, not bits.
|
2017-03-17 11:16:46 +00:00 |
|
moninj.py
|
moninj: do not require a rsys clock domain
|
2017-02-20 15:52:48 +08:00 |
