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artiq/artiq/gateware/drtio
mwojcik f281112779 satman: add 100mhz si5324 settings
siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
..
transceiver made kc705/gtx interface more similar to kasli/gtp 2021-08-10 18:53:52 +08:00
wrpll wrpll: separate collector reset 2020-11-09 17:57:13 +08:00
__init__.py drtio: separate aux controller 2018-09-05 17:56:58 +08:00
aux_controller.py drtio: accept 32b/64b bus 2021-11-08 16:59:08 +08:00
cdc.py add missing files 2018-09-05 16:09:02 +08:00
core.py sayma: fix/cleanup DRTIO-DAC sync interaction 2020-04-06 22:34:05 +08:00
link_layer.py drtio: raise RTIOLinkError if operation fails due to link lost (#942) 2018-03-04 01:02:53 +08:00
rt_controller_master.py gateware,runtime: optimize RTIO kernel interface further 2018-11-08 18:29:24 +08:00
rt_controller_repeater.py rtio: use BlindTransfer from Migen 2019-07-05 18:46:18 +08:00
rt_errors_satellite.py rtio: use BlindTransfer from Migen 2019-07-05 18:46:18 +08:00
rt_packet_master.py rtio: use BlindTransfer from Migen 2019-07-05 18:46:18 +08:00
rt_packet_repeater.py drtio: 8-bit address 2018-11-08 18:36:20 +08:00
rt_packet_satellite.py gateware,runtime: optimize RTIO kernel interface further 2018-11-08 18:29:24 +08:00
rt_serializer.py drtio: 8-bit address 2018-11-08 18:36:20 +08:00
rx_synchronizer.py siphaser: autocalibrate skew using RX synchronizer 2019-01-02 22:29:27 +08:00
siphaser.py satman: add 100mhz si5324 settings 2021-12-03 17:19:11 +08:00