forked from M-Labs/artiq
Robert Jordens
219dfd8984
* This should give Vivado some wiggle room during PnR. * It needs three new clock domains which is ugly. But since AsyncResetSynchronizer can only drive clock domains resets directly there seems to be no other way to add one register level currently. |
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.. | ||
phy | ||
__init__.py | ||
analyzer.py | ||
cdc.py | ||
core.py | ||
cri.py | ||
dma.py | ||
moninj.py | ||
rtlink.py |