artiq/artiq/gateware/rtio
Robert Jordens 219dfd8984 rtio: add one register level for rio and rio_phy resets
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
..
phy Remove Pipistrello support 2017-05-15 17:17:44 +08:00
__init__.py rtio: export DMA and CRIInterconnectShared 2016-12-01 16:30:29 +08:00
analyzer.py make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads 2017-03-27 16:32:23 +08:00
cdc.py drtio: use BlindTransfer for error reporting 2017-04-03 00:18:07 +08:00
core.py rtio: add one register level for rio and rio_phy resets 2017-06-17 12:17:48 +02:00
cri.py cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
dma.py gateware: simplify the CRI arbiter to use a plain mux. 2017-04-05 15:09:19 +00:00
moninj.py moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
rtlink.py rtio: add support for latency compensation in phy 2016-12-14 19:16:07 +01:00