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artiq/artiq/gateware/rtio
Sebastien Bourdeauducq cf9cf0ab6f ttl_serdes_7series: add dci (HP bank) support 2021-02-07 22:32:18 +08:00
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phy ttl_serdes_7series: add dci (HP bank) support 2021-02-07 22:32:18 +08:00
sed gateware,runtime: optimize RTIO kernel interface further 2018-11-08 18:29:24 +08:00
__init__.py cri: fix firmware routing table access 2018-09-12 18:08:16 +08:00
analyzer.py gateware,runtime: optimize RTIO kernel interface further 2018-11-08 18:29:24 +08:00
cdc.py rtio: use BlindTransfer from Migen 2019-07-05 18:46:18 +08:00
channel.py use FutureWarning instead of DeprecationWarning 2018-10-21 12:14:51 +08:00
core.py rtio: use BlindTransfer from Migen 2019-07-05 18:46:18 +08:00
cri.py rtio: remove legacy i_overflow_reset CSR 2020-08-06 17:52:32 +08:00
dma.py rtio/dma: fix previous commit 2020-07-12 10:14:22 +08:00
input_collector.py rtio: use BlindTransfer from Migen 2019-07-05 18:46:18 +08:00
moninj.py moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
rtlink.py rtlink: sanity-check parameters 2018-11-26 01:14:02 +08:00
tsc.py add missing files 2018-09-05 16:09:02 +08:00