Sebastien Bourdeauducq 3bd190e624 gateware/nist_clock: increase DDS bus drive strength. Closes #468		2016-06-07 11:08:19 -04:00
..
amp	Implement core device storage (fixes #219).	2016-01-10 13:04:55 +00:00
rtio	analyzer: make byte_count 64-bit	2016-03-19 19:40:23 +08:00
targets	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9xxx.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc1.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
soc.py	soc: use add_extra_software_packages, factor builder code	2016-03-07 00:18:47 +08:00
spi.py	gateware.spi: delay only writes to data register, update doc	2016-03-01 14:14:38 +01:00