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artiq/artiq/gateware/drtio
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Sebastien Bourdeauducq f060d6e1b3 drtio: increase A7 clock aligner check period
2018-02-20 18:50:35 +08:00
..
transceiver drtio: increase A7 clock aligner check period 2018-02-20 18:50:35 +08:00
__init__.py drtio: structure 2016-10-10 23:12:12 +08:00
aux_controller.py drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
core.py drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
link_layer.py drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
rt_controller_master.py drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
rt_errors_satellite.py rtio: report channel numbers in asynchronous errors 2017-09-29 16:32:57 +08:00
rt_packet_master.py drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
rt_packet_satellite.py drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
rt_serializer.py drtio: rewrite/fix reset and link bringup/teardown 2018-02-20 17:26:43 +08:00
xilinx_rx_synchronizer.py drtio: add Xilinx RX synchronizer 2018-02-19 17:49:43 +08:00