Robert Jordens 0bd54921af move default TCP ports from 8887... to 3250... ... * 8888 is busy: IPython default among others * 3250 seems less so and is the house number times ten here		2015-01-13 10:56:44 +08:00
..
conf.py	manual: use theme options which looks like m-labs web site	2014-12-02 10:32:27 +08:00
core_drivers_reference.rst	doc: some precisions about controllers	2014-10-28 11:43:06 +08:00
core_language_reference.rst	doc/manual: minor fixes	2014-12-02 19:23:15 +08:00
drivers_reference.rst	move default TCP ports from 8887... to 3250...	2015-01-13 10:56:44 +08:00
fpga_board_ports.rst	targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG	2014-12-01 18:53:29 +08:00
getting_started.rst	refactor device/parameter management, immediate parameter updates, start introducing results	2015-01-12 18:51:23 +08:00
index.rst	doc/manual: add ports to index	2014-11-21 18:08:40 -08:00
installing.rst	update dependencies	2014-12-20 12:14:27 +08:00
Makefile	doc: add sphinx infrastructure	2014-09-18 17:45:54 +08:00
management_reference.rst	doc: minor fixes	2015-01-05 16:12:35 +08:00
writing_a_driver.rst	refactor device/parameter management, immediate parameter updates, start introducing results	2015-01-12 18:51:23 +08:00