forked from M-Labs/artiq
547 lines
18 KiB
Python
547 lines
18 KiB
Python
from types import SimpleNamespace
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.cdc import PulseSynchronizer
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def layout_len(l):
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return sum(e[1] for e in l)
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class PacketLayoutManager:
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def __init__(self, alignment):
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self.alignment = alignment
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self.layouts = dict()
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self.types = dict()
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self.type_names = dict()
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def add_type(self, name, *fields, pad=True):
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type_n = len(self.types)
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self.types[name] = type_n
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self.type_names[type_n] = name
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layout = [("ty", 8)] + list(fields)
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misalignment = layout_len(layout) % self.alignment
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if misalignment:
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layout.append(("packet_pad", self.alignment - misalignment))
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self.layouts[name] = layout
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def get_m2s_layouts(alignment):
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plm = PacketLayoutManager(alignment)
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plm.add_type("echo_request")
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plm.add_type("set_time", ("timestamp", 64))
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plm.add_type("write", ("timestamp", 64),
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("channel", 16),
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("address", 16),
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("data_len", 8),
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("short_data", 8))
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plm.add_type("fifo_space_request", ("channel", 16))
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return plm
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def get_s2m_layouts(alignment):
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plm = PacketLayoutManager(alignment)
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plm.add_type("error", ("code", 8))
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plm.add_type("echo_reply")
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plm.add_type("fifo_space_reply", ("space", 16))
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return plm
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error_codes = {
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"unknown_type": 0,
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# The transmitter is normally responsible for avoiding
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# overflows and underflows. Those error reports are only
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# for diagnosing internal ARTIQ bugs.
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"write_overflow": 1,
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"write_underflow": 2
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}
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class ReceiveDatapath(Module):
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def __init__(self, frame, data, plm):
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ws = len(data)
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# control
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self.packet_buffer_load = Signal()
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# outputs
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self.frame_r = Signal()
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self.data_r = Signal(ws)
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self.packet_type = Signal(8)
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self.packet_last = Signal()
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self.packet_as = dict()
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# # #
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# input pipeline stage - determine packet length based on type
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lastword_per_type = [layout_len(plm.layouts[plm.type_names[i]])//ws - 1
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for i in range(len(plm.layouts))]
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packet_last_n = Signal(max=max(lastword_per_type)+1)
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self.sync += [
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self.frame_r.eq(frame),
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self.data_r.eq(data),
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If(frame & ~self.frame_r,
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self.packet_type.eq(data[:8]),
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packet_last_n.eq(Array(lastword_per_type)[data[:8]])
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)
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]
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# bufferize packet
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packet_buffer = Signal(max(layout_len(l)
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for l in plm.layouts.values()))
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w_in_packet = len(packet_buffer)//ws
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packet_buffer_count = Signal(max=w_in_packet+1)
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self.sync += \
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If(self.packet_buffer_load,
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Case(packet_buffer_count,
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{i: packet_buffer[i*ws:(i+1)*ws].eq(self.data_r)
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for i in range(w_in_packet)}),
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packet_buffer_count.eq(packet_buffer_count + 1)
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).Else(
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packet_buffer_count.eq(0)
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)
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self.comb += self.packet_last.eq(packet_buffer_count == packet_last_n)
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# dissect packet
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for name, layout in plm.layouts.items():
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fields = SimpleNamespace()
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idx = 0
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for field_name, field_size in layout:
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setattr(fields, field_name, packet_buffer[idx:idx+field_size])
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idx += field_size
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self.packet_as[name] = fields
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class TransmitDatapath(Module):
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def __init__(self, frame, data, plm):
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ws = len(data)
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assert ws % 8 == 0
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self.ws = ws
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self.plm = plm
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# inputs
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self.packet_buffer = Signal(max(layout_len(l)
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for l in plm.layouts.values()))
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w_in_packet = len(self.packet_buffer)//ws
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self.packet_len = Signal(max=w_in_packet+1)
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# control
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self.stb = Signal()
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self.done = Signal()
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# # #
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packet_buffer_count = Signal(max=w_in_packet+1)
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self.sync += [
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self.done.eq(0),
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frame.eq(0),
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packet_buffer_count.eq(0),
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If(self.stb & ~self.done,
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If(packet_buffer_count == self.packet_len,
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self.done.eq(1)
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).Else(
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frame.eq(1),
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Case(packet_buffer_count,
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{i: data.eq(self.packet_buffer[i*ws:(i+1)*ws])
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for i in range(w_in_packet)}),
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packet_buffer_count.eq(packet_buffer_count + 1)
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)
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)
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]
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def send(self, ty, **kwargs):
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idx = 8
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value = self.plm.types[ty]
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for field_name, field_size in self.plm.layouts[ty][1:]:
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try:
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fvalue = kwargs[field_name]
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del kwargs[field_name]
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except KeyError:
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fvalue = 0
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value = value | (fvalue << idx)
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idx += field_size
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if kwargs:
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raise ValueError
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return [
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self.packet_buffer.eq(value),
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self.packet_len.eq(idx//self.ws)
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]
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class RTPacketSatellite(Module):
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def __init__(self, link_layer):
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self.tsc_load = Signal()
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self.tsc_value = Signal(64)
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self.fifo_space_channel = Signal(16)
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self.fifo_space_update = Signal()
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self.fifo_space = Signal(16)
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self.write_stb = Signal()
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self.write_timestamp = Signal(64)
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self.write_channel = Signal(16)
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self.write_address = Signal(16)
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self.write_data = Signal(256)
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self.write_overflow = Signal()
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self.write_overflow_ack = Signal()
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self.write_underflow = Signal()
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self.write_underflow_ack = Signal()
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# # #
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# RX/TX datapath
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assert len(link_layer.tx_rt_data) == len(link_layer.rx_rt_data)
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assert len(link_layer.tx_rt_data) % 8 == 0
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ws = len(link_layer.tx_rt_data)
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rx_plm = get_m2s_layouts(ws)
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rx_dp = ReceiveDatapath(
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link_layer.rx_rt_frame, link_layer.rx_rt_data, rx_plm)
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self.submodules += rx_dp
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tx_plm = get_s2m_layouts(ws)
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tx_dp = TransmitDatapath(
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link_layer.tx_rt_frame, link_layer.tx_rt_data, tx_plm)
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self.submodules += tx_dp
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# RX->TX
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echo_req = Signal()
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err_set = Signal()
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err_req = Signal()
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err_ack = Signal()
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fifo_space_set = Signal()
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fifo_space_req = Signal()
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fifo_space_ack = Signal()
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self.sync += [
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If(err_ack, err_req.eq(0)),
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If(err_set, err_req.eq(1)),
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If(fifo_space_ack, fifo_space_req.eq(0)),
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If(fifo_space_set, fifo_space_req.eq(1)),
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]
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err_code = Signal(max=len(error_codes)+1)
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# RX FSM
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self.comb += [
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self.tsc_value.eq(
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rx_dp.packet_as["set_time"].timestamp),
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self.fifo_space_channel.eq(
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rx_dp.packet_as["fifo_space_request"].channel),
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self.write_timestamp.eq(
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rx_dp.packet_as["write"].timestamp),
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self.write_channel.eq(
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rx_dp.packet_as["write"].channel),
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self.write_address.eq(
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rx_dp.packet_as["write"].address),
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self.write_data.eq(
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rx_dp.packet_as["write"].short_data)
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]
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rx_fsm = FSM(reset_state="INPUT")
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self.submodules += rx_fsm
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rx_fsm.act("INPUT",
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If(rx_dp.frame_r,
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rx_dp.packet_buffer_load.eq(1),
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If(rx_dp.packet_last,
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Case(rx_dp.packet_type, {
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# echo must have fixed latency, so there is no memory
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# mechanism
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rx_plm.types["echo_request"]: echo_req.eq(1),
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rx_plm.types["set_time"]: NextState("SET_TIME"),
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rx_plm.types["write"]: NextState("WRITE"),
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rx_plm.types["fifo_space_request"]:
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NextState("FIFO_SPACE"),
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"default": [
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err_set.eq(1),
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NextValue(err_code, error_codes["unknown_type"])]
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})
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)
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)
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)
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rx_fsm.act("SET_TIME",
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self.tsc_load.eq(1),
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NextState("INPUT")
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)
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rx_fsm.act("WRITE",
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self.write_stb.eq(1),
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NextState("INPUT")
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)
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rx_fsm.act("FIFO_SPACE",
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fifo_space_set.eq(1),
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self.fifo_space_update.eq(1),
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NextState("INPUT")
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)
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# TX FSM
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tx_fsm = FSM(reset_state="IDLE")
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self.submodules += tx_fsm
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tx_fsm.act("IDLE",
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If(echo_req, NextState("ECHO")),
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If(fifo_space_req, NextState("FIFO_SPACE")),
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If(self.write_overflow, NextState("ERROR_WRITE_OVERFLOW")),
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If(self.write_underflow, NextState("ERROR_WRITE_UNDERFLOW")),
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If(err_req, NextState("ERROR"))
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)
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tx_fsm.act("ECHO",
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tx_dp.send("echo_reply"),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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)
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tx_fsm.act("FIFO_SPACE",
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fifo_space_ack.eq(1),
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tx_dp.send("fifo_space_reply", space=self.fifo_space),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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)
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tx_fsm.act("ERROR_WRITE_OVERFLOW",
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self.write_overflow_ack.eq(1),
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tx_dp.send("error", code=error_codes["write_overflow"]),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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)
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tx_fsm.act("ERROR_WRITE_UNDERFLOW",
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self.write_underflow_ack.eq(1),
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tx_dp.send("error", code=error_codes["write_underflow"]),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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)
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tx_fsm.act("ERROR",
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err_ack.eq(1),
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tx_dp.send("error", code=err_code),
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tx_dp.stb.eq(1),
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If(tx_dp.done, NextState("IDLE"))
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)
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class _CrossDomainRequest(Module):
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def __init__(self, domain,
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req_stb, req_ack, req_data,
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srv_stb, srv_ack, srv_data):
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dsync = getattr(self.sync, domain)
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request = PulseSynchronizer("sys", domain)
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reply = PulseSynchronizer(domain, "sys")
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self.submodules += request, reply
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ongoing = Signal()
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self.comb += request.i.eq(~ongoing & req_stb)
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self.sync += [
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req_ack.eq(reply.o),
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If(req_stb, ongoing.eq(1)),
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If(req_ack, ongoing.eq(0))
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]
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if req_data is not None:
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req_data_r = Signal.like(req_data)
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req_data_r.attr.add("no_retiming")
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self.sync += If(req_stb, req_data_r.eq(req_data))
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dsync += [
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If(request.o, srv_stb.eq(1)),
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If(srv_ack, srv_stb.eq(0))
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]
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if req_data is not None:
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dsync += If(request.o, srv_data.eq(req_data_r))
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self.comb += reply.i.eq(srv_stb & srv_ack)
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class _CrossDomainNotification(Module):
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def __init__(self, domain,
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emi_stb, emi_data,
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rec_stb, rec_ack, rec_data):
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emi_data_r = Signal.like(emi_data)
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emi_data_r.attr.add("no_retiming")
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dsync = getattr(self.sync, domain)
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dsync += If(emi_stb, emi_data_r.eq(emi_data))
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ps = PulseSynchronizer(domain, "sys")
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self.submodules += ps
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self.comb += ps.i.eq(emi_stb)
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self.sync += [
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If(rec_ack, rec_stb.eq(0)),
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If(ps.o,
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rec_data.eq(emi_data_r),
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rec_stb.eq(1)
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)
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]
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class RTPacketMaster(Module):
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def __init__(self, link_layer, write_fifo_depth=4):
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# all interface signals in sys domain unless otherwise specified
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# write interface, optimized for throughput
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self.write_stb = Signal()
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self.write_ack = Signal()
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self.write_timestamp = Signal(64)
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self.write_channel = Signal(16)
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self.write_address = Signal(16)
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self.write_data = Signal(256)
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# fifo space interface
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# write with timestamp[48:] == 0xffff to make a fifo space request
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# (space requests have to be ordered wrt writes)
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self.fifo_space_not = Signal()
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self.fifo_space_not_ack = Signal()
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self.fifo_space = Signal(16)
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# echo interface
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self.echo_stb = Signal()
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self.echo_ack = Signal()
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self.echo_sent_now = Signal() # in rtio domain
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self.echo_received_now = Signal() # in rtio_rx domain
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# set_time interface
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self.set_time_stb = Signal()
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self.set_time_ack = Signal()
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# in rtio domain, must be valid all time while there is
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# a set_time request pending
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self.tsc_value = Signal(64)
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# errors
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self.error_not = Signal()
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self.error_not_ack = Signal()
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self.error_code = Signal(8)
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# # #
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# CDC
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wfifo = ClockDomainsRenamer({"write": "sys", "read": "rtio"})(
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AsyncFIFO(64+16+16+256, write_fifo_depth))
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self.submodules += wfifo
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write_timestamp = Signal(64)
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write_channel = Signal(16)
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write_address = Signal(16)
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write_data = Signal(256)
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self.comb += [
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wfifo.we.eq(self.write_stb),
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self.write_ack.eq(wfifo.writable),
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wfifo.din.eq(Cat(self.write_timestamp, self.write_channel,
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self.write_address, self.write_data)),
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Cat(write_timestamp, write_channel,
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write_address, write_data).eq(wfifo.dout)
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]
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fifo_space_not = Signal()
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fifo_space = Signal(16)
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self.submodules += _CrossDomainNotification("rtio_rx",
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fifo_space_not, fifo_space,
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self.fifo_space_not, self.fifo_space_not_ack, self.fifo_space)
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set_time_stb = Signal()
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set_time_ack = Signal()
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self.submodules += _CrossDomainRequest("rtio",
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self.set_time_stb, self.set_time_ack, None,
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set_time_stb, set_time_ack, None)
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echo_stb = Signal()
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echo_ack = Signal()
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self.submodules += _CrossDomainRequest("rtio",
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self.echo_stb, self.echo_ack, None,
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echo_stb, echo_ack, None)
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error_not = Signal()
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error_code = Signal(8)
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self.submodules += _CrossDomainNotification("rtio_rx",
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error_not, error_code,
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self.error_not, self.error_not_ack, self.error_code)
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# RX/TX datapath
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assert len(link_layer.tx_rt_data) == len(link_layer.rx_rt_data)
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assert len(link_layer.tx_rt_data) % 8 == 0
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ws = len(link_layer.tx_rt_data)
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tx_plm = get_m2s_layouts(ws)
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tx_dp = ClockDomainsRenamer("rtio")(TransmitDatapath(
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link_layer.tx_rt_frame, link_layer.tx_rt_data, tx_plm))
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self.submodules += tx_dp
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rx_plm = get_s2m_layouts(ws)
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rx_dp = ClockDomainsRenamer("rtio_rx")(ReceiveDatapath(
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link_layer.rx_rt_frame, link_layer.rx_rt_data, rx_plm))
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self.submodules += rx_dp
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# TX FSM
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tx_fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="IDLE_WRITE"))
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self.submodules += tx_fsm
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echo_sent_now = Signal()
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self.sync.rtio += self.echo_sent_now.eq(echo_sent_now)
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tsc_value = Signal(64)
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tsc_value_load = Signal()
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self.sync.rtio += If(tsc_value_load, tsc_value.eq(self.tsc_value))
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tx_fsm.act("IDLE_WRITE",
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tx_dp.send("write",
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timestamp=write_timestamp,
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channel=write_channel,
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address=write_address,
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short_data=write_data),
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If(wfifo.readable,
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If(write_timestamp[48:] == 0xffff,
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NextState("FIFO_SPACE")
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).Else(
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tx_dp.stb.eq(1),
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wfifo.re.eq(tx_dp.done)
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)
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).Else(
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If(echo_stb,
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echo_sent_now.eq(1),
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NextState("ECHO")
|
|
).Elif(set_time_stb,
|
|
tsc_value_load.eq(1),
|
|
NextState("SET_TIME")
|
|
)
|
|
)
|
|
)
|
|
tx_fsm.act("FIFO_SPACE",
|
|
tx_dp.send("fifo_space_request", channel=write_channel),
|
|
tx_dp.stb.eq(1),
|
|
If(tx_dp.done,
|
|
wfifo.re.eq(1),
|
|
NextState("IDLE_WRITE")
|
|
)
|
|
)
|
|
tx_fsm.act("ECHO",
|
|
tx_dp.send("echo_request"),
|
|
tx_dp.stb.eq(1),
|
|
If(tx_dp.done, NextState("IDLE_WRITE"))
|
|
)
|
|
tx_fsm.act("SET_TIME",
|
|
tx_dp.send("set_time", timestamp=tsc_value),
|
|
tx_dp.stb.eq(1),
|
|
If(tx_dp.done, NextState("IDLE_WRITE"))
|
|
)
|
|
|
|
# RX FSM
|
|
rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))
|
|
self.submodules += rx_fsm
|
|
|
|
echo_received_now = Signal()
|
|
self.sync.rtio_rx += self.echo_received_now.eq(echo_received_now)
|
|
|
|
rx_fsm.act("INPUT",
|
|
If(rx_dp.frame_r,
|
|
rx_dp.packet_buffer_load.eq(1),
|
|
If(rx_dp.packet_last,
|
|
Case(rx_dp.packet_type, {
|
|
rx_plm.types["error"]: NextState("ERROR"),
|
|
rx_plm.types["echo_reply"]: echo_received_now.eq(1),
|
|
rx_plm.types["fifo_space_reply"]: NextState("FIFO_SPACE"),
|
|
"default": [
|
|
error_not.eq(1),
|
|
error_code.eq(error_codes["unknown_type"])
|
|
]
|
|
})
|
|
)
|
|
)
|
|
)
|
|
rx_fsm.act("ERROR",
|
|
error_not.eq(1),
|
|
error_code.eq(rx_dp.packet_as["error"].code),
|
|
NextState("INPUT")
|
|
)
|
|
rx_fsm.act("FIFO_SPACE",
|
|
fifo_space_not.eq(1),
|
|
fifo_space.eq(rx_dp.packet_as["fifo_space_reply"].space),
|
|
NextState("INPUT")
|
|
)
|