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f03ae5e5b0
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soc/rtio: separate PHY, add OE and fine timestamp in FIFO
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2014-07-24 23:50:20 -06:00 |
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005d66c7cd
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soc/dds: fix timing
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2014-07-22 17:44:41 -06:00 |
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2358b218bf
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soc: add DDS interface core
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2014-07-22 11:37:53 -06:00 |
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cdda1beea8
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soc/rtio: refactor, share counter and underflow detector
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2014-07-21 13:17:21 -06:00 |
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5f58789592
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rtio: fix FIFO WE
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2014-07-20 18:22:53 -06:00 |
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0cb18d58a8
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rtio: add FIFO level CSR
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2014-07-17 19:35:53 -06:00 |
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3b4bb41a19
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add basic output-only untested RTIO core
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2014-07-16 19:13:11 -06:00 |
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