occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

rtio: remove unused clk_freq argument

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2015-07-27 10:57:15 +08:00
parent 5b50f5fe05
commit fe6a5c42df
3 changed files with 3 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
artiq/gateware/rtio/core.py
View File

@ -300,8 +300,7 @@ class _KernelCSRs(AutoCSR):
class RTIO(Module):
def __init__(self, channels, clk_freq, full_ts_width=63,
guard_io_cycles=20):
def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
data_width = max(rtlink.get_data_width(c.interface)
for c in channels)
address_width = max(rtlink.get_address_width(c.interface)

3
soc/targets/artiq_kc705.py
View File

@ -58,8 +58,7 @@ class _NIST_QCx(MiniSoC, AMPSoC):
def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.pll_sys)
self.submodules.rtio = rtio.RTIO(rtio_channels,
clk_freq=125000000)
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)

3
soc/targets/artiq_pipistrello.py
View File

@ -128,8 +128,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
# RTIO core
self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
self.submodules.rtio = rtio.RTIO(rtio_channels,
clk_freq=125000000)
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)