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tests: make hardware-in-the loop flags positive logic

Explicitly having to disable unittests that require hardware
(ARTIQ_NO_HARDWARE) is cumbersome.
There is not even a sensible default for the
device or serial number of the devices requiring additional
variables (ARTIQ_LDA_DEVICE etc).

This patch reverts the logic by skipping unittests that
can not automatically determine whether the required hardware
is present and where it is.
This commit is contained in:
Robert Jördens 2015-04-02 02:20:02 -06:00 committed by Sebastien Bourdeauducq
parent 2995f0a705
commit fb91955260
4 changed files with 23 additions and 32 deletions

View File

@ -7,7 +7,6 @@ env:
- PATH=$HOME/miniconda/bin:/usr/local/llvm-or1k/bin:$PATH - PATH=$HOME/miniconda/bin:/usr/local/llvm-or1k/bin:$PATH
- CC=gcc-4.7 - CC=gcc-4.7
- CXX=g++-4.7 - CXX=g++-4.7
- ARTIQ_NO_HARDWARE=1
- BUILD_SOC=1 - BUILD_SOC=1
- secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws=" - secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws="
before_install: before_install:

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@ -9,11 +9,11 @@ from artiq.coredevice import comm_serial, core, runtime_exceptions, rtio
from artiq.sim import devices as sim_devices from artiq.sim import devices as sim_devices
no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE")) core_device = os.getenv("ARTIQ_CORE_DEVICE")
def _run_on_device(k_class, **parameters): def _run_on_device(k_class, **parameters):
comm = comm_serial.Comm() comm = comm_serial.Comm(serial_dev=core_device)
try: try:
coredev = core.Core(comm=comm) coredev = core.Core(comm=comm)
k_inst = k_class(core=coredev, **parameters) k_inst = k_class(core=coredev, **parameters)
@ -199,7 +199,7 @@ class _RPCExceptions(AutoDB):
self.success = True self.success = True
@unittest.skipIf(no_hardware, "no hardware") @unittest.skipUnless(core_device, "no hardware")
class ExecutionCase(unittest.TestCase): class ExecutionCase(unittest.TestCase):
def test_primes(self): def test_primes(self):
l_device, l_host = [], [] l_device, l_host = [], []
@ -208,7 +208,7 @@ class ExecutionCase(unittest.TestCase):
self.assertEqual(l_device, l_host) self.assertEqual(l_device, l_host)
def test_misc(self): def test_misc(self):
comm = comm_serial.Comm() comm = comm_serial.Comm(serial_dev=core_device)
try: try:
coredev = core.Core(comm=comm) coredev = core.Core(comm=comm)
uut = _Misc(core=coredev) uut = _Misc(core=coredev)
@ -249,7 +249,7 @@ class ExecutionCase(unittest.TestCase):
self.assertEqual(t_device, t_host) self.assertEqual(t_device, t_host)
def test_rpc_exceptions(self): def test_rpc_exceptions(self):
comm = comm_serial.Comm() comm = comm_serial.Comm(serial_dev=core_device)
try: try:
uut = _RPCExceptions(core=core.Core(comm=comm)) uut = _RPCExceptions(core=core.Core(comm=comm))
with self.assertRaises(_MyException): with self.assertRaises(_MyException):
@ -306,13 +306,13 @@ class _RTIOSequenceError(AutoDB):
self.o.pulse(25*us) self.o.pulse(25*us)
@unittest.skipIf(no_hardware, "no hardware") @unittest.skipUnless(core_device, "no hardware")
class RTIOCase(unittest.TestCase): class RTIOCase(unittest.TestCase):
# Connect channels 0 and 1 together for this test # Connect channels 0 and 1 together for this test
# (C11 and C13 on Papilio Pro) # (C11 and C13 on Papilio Pro)
def test_loopback(self): def test_loopback(self):
npulses = 4 npulses = 4
comm = comm_serial.Comm() comm = comm_serial.Comm(serial_dev=core_device)
try: try:
coredev = core.Core(comm=comm) coredev = core.Core(comm=comm)
uut = _RTIOLoopback( uut = _RTIOLoopback(
@ -327,7 +327,7 @@ class RTIOCase(unittest.TestCase):
comm.close() comm.close()
def test_underflow(self): def test_underflow(self):
comm = comm_serial.Comm() comm = comm_serial.Comm(serial_dev=core_device)
try: try:
coredev = core.Core(comm=comm) coredev = core.Core(comm=comm)
uut = _RTIOUnderflow( uut = _RTIOUnderflow(
@ -340,7 +340,7 @@ class RTIOCase(unittest.TestCase):
comm.close() comm.close()
def test_sequence_error(self): def test_sequence_error(self):
comm = comm_serial.Comm() comm = comm_serial.Comm(serial_dev=core_device)
try: try:
coredev = core.Core(comm=comm) coredev = core.Core(comm=comm)
uut = _RTIOSequenceError( uut = _RTIOSequenceError(

View File

@ -5,8 +5,7 @@ from artiq.devices.lda.driver import Lda, Ldasim
from artiq.language.units import dB from artiq.language.units import dB
no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE")) \ lda_serial = os.getenv("ARTIQ_LDA_SERIAL")
or bool(os.getenv("ARTIQ_NO_PERIPHERALS"))
class GenericLdaTest: class GenericLdaTest:
@ -20,18 +19,11 @@ class GenericLdaTest:
self.assertEqual(i, self.cont.get_attenuation()) self.assertEqual(i, self.cont.get_attenuation())
@unittest.skipIf(no_hardware, "no hardware") @unittest.skipUnless(lda_serial, "no hardware")
class TestLda(GenericLdaTest, unittest.TestCase): class TestLda(GenericLdaTest, unittest.TestCase):
def setUp(self): def setUp(self):
device = os.getenv("ARTIQ_LDA_DEVICE") product = os.getenv("ARTIQ_LDA_PRODUCT")
serial = os.getenv("ARTIQ_LDA_SERIAL") self.cont = Lda(serial=lda_serial, product=product)
args = dict()
if device is not None:
args["product"] = device
if serial is not None:
args["serial"] = serial
self.cont = Lda(**args)
class TestLdaSim(GenericLdaTest, unittest.TestCase): class TestLdaSim(GenericLdaTest, unittest.TestCase):

View File

@ -6,10 +6,6 @@ from artiq.devices.thorlabs_tcube.driver import Tdc, Tpz, TdcSim, TpzSim
from artiq.language.units import V from artiq.language.units import V
no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE")) \
or bool(os.getenv("ARTIQ_NO_PERIPHERALS"))
class GenericTdcTest: class GenericTdcTest:
def test_pot_parameters(self): def test_pot_parameters(self):
test_vector = 1, 2, 3, 4, 5, 6, 7, 8 test_vector = 1, 2, 3, 4, 5, 6, 7, 8
@ -135,11 +131,13 @@ class GenericTpzTest:
self.assertEqual(test_vector, self.cont.get_tpz_io_settings()) self.assertEqual(test_vector, self.cont.get_tpz_io_settings())
@unittest.skipIf(no_hardware, "no hardware") tdc_serial = os.getenv("ARTIQ_TDC_SERIAL")
@unittest.skipUnless(tdc_serial, "no hardware")
class TestTdc(unittest.TestCase, GenericTdcTest): class TestTdc(unittest.TestCase, GenericTdcTest):
def setUp(self): def setUp(self):
serial_dev = os.getenv("ARTIQ_TDC001_SERIAL", "/dev/ttyUSB0") self.cont = Tdc(serial_dev=tdc_serial)
self.cont = Tdc(serial_dev=serial_dev)
class TestTdcSim(unittest.TestCase, GenericTdcTest): class TestTdcSim(unittest.TestCase, GenericTdcTest):
@ -147,11 +145,13 @@ class TestTdcSim(unittest.TestCase, GenericTdcTest):
self.cont = TdcSim() self.cont = TdcSim()
@unittest.skipIf(no_hardware, "no hardware") tpz_serial = os.getenv("ARTIQ_TPZ_SERIAL")
@unittest.skipUnless(tpz_serial, "no hardware")
class TestTpz(unittest.TestCase, GenericTpzTest): class TestTpz(unittest.TestCase, GenericTpzTest):
def setUp(self): def setUp(self):
serial_dev = os.getenv("ARTIQ_TPZ001_SERIAL", "/dev/ttyUSB0") self.cont = Tpz(serial_dev=tpz_serial)
self.cont = Tpz(serial_dev=serial_dev)
class TestTpzSim(unittest.TestCase, GenericTpzTest): class TestTpzSim(unittest.TestCase, GenericTpzTest):