forked from M-Labs/artiq
tests: make hardware-in-the loop flags positive logic
Explicitly having to disable unittests that require hardware (ARTIQ_NO_HARDWARE) is cumbersome. There is not even a sensible default for the device or serial number of the devices requiring additional variables (ARTIQ_LDA_DEVICE etc). This patch reverts the logic by skipping unittests that can not automatically determine whether the required hardware is present and where it is.
This commit is contained in:
parent
2995f0a705
commit
fb91955260
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@ -7,7 +7,6 @@ env:
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- PATH=$HOME/miniconda/bin:/usr/local/llvm-or1k/bin:$PATH
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- PATH=$HOME/miniconda/bin:/usr/local/llvm-or1k/bin:$PATH
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- CC=gcc-4.7
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- CC=gcc-4.7
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- CXX=g++-4.7
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- CXX=g++-4.7
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- ARTIQ_NO_HARDWARE=1
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- BUILD_SOC=1
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- BUILD_SOC=1
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- secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws="
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- secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws="
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before_install:
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before_install:
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@ -9,11 +9,11 @@ from artiq.coredevice import comm_serial, core, runtime_exceptions, rtio
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from artiq.sim import devices as sim_devices
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from artiq.sim import devices as sim_devices
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no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE"))
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core_device = os.getenv("ARTIQ_CORE_DEVICE")
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def _run_on_device(k_class, **parameters):
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def _run_on_device(k_class, **parameters):
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comm = comm_serial.Comm()
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comm = comm_serial.Comm(serial_dev=core_device)
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try:
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try:
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coredev = core.Core(comm=comm)
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coredev = core.Core(comm=comm)
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k_inst = k_class(core=coredev, **parameters)
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k_inst = k_class(core=coredev, **parameters)
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@ -199,7 +199,7 @@ class _RPCExceptions(AutoDB):
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self.success = True
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self.success = True
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@unittest.skipIf(no_hardware, "no hardware")
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@unittest.skipUnless(core_device, "no hardware")
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class ExecutionCase(unittest.TestCase):
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class ExecutionCase(unittest.TestCase):
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def test_primes(self):
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def test_primes(self):
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l_device, l_host = [], []
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l_device, l_host = [], []
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@ -208,7 +208,7 @@ class ExecutionCase(unittest.TestCase):
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self.assertEqual(l_device, l_host)
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self.assertEqual(l_device, l_host)
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def test_misc(self):
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def test_misc(self):
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comm = comm_serial.Comm()
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comm = comm_serial.Comm(serial_dev=core_device)
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try:
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try:
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coredev = core.Core(comm=comm)
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coredev = core.Core(comm=comm)
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uut = _Misc(core=coredev)
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uut = _Misc(core=coredev)
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@ -249,7 +249,7 @@ class ExecutionCase(unittest.TestCase):
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self.assertEqual(t_device, t_host)
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self.assertEqual(t_device, t_host)
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def test_rpc_exceptions(self):
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def test_rpc_exceptions(self):
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comm = comm_serial.Comm()
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comm = comm_serial.Comm(serial_dev=core_device)
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try:
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try:
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uut = _RPCExceptions(core=core.Core(comm=comm))
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uut = _RPCExceptions(core=core.Core(comm=comm))
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with self.assertRaises(_MyException):
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with self.assertRaises(_MyException):
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@ -306,13 +306,13 @@ class _RTIOSequenceError(AutoDB):
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self.o.pulse(25*us)
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self.o.pulse(25*us)
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@unittest.skipIf(no_hardware, "no hardware")
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@unittest.skipUnless(core_device, "no hardware")
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class RTIOCase(unittest.TestCase):
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class RTIOCase(unittest.TestCase):
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# Connect channels 0 and 1 together for this test
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# Connect channels 0 and 1 together for this test
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# (C11 and C13 on Papilio Pro)
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# (C11 and C13 on Papilio Pro)
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def test_loopback(self):
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def test_loopback(self):
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npulses = 4
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npulses = 4
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comm = comm_serial.Comm()
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comm = comm_serial.Comm(serial_dev=core_device)
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try:
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try:
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coredev = core.Core(comm=comm)
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coredev = core.Core(comm=comm)
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uut = _RTIOLoopback(
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uut = _RTIOLoopback(
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@ -327,7 +327,7 @@ class RTIOCase(unittest.TestCase):
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comm.close()
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comm.close()
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def test_underflow(self):
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def test_underflow(self):
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comm = comm_serial.Comm()
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comm = comm_serial.Comm(serial_dev=core_device)
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try:
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try:
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coredev = core.Core(comm=comm)
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coredev = core.Core(comm=comm)
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uut = _RTIOUnderflow(
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uut = _RTIOUnderflow(
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@ -340,7 +340,7 @@ class RTIOCase(unittest.TestCase):
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comm.close()
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comm.close()
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def test_sequence_error(self):
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def test_sequence_error(self):
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comm = comm_serial.Comm()
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comm = comm_serial.Comm(serial_dev=core_device)
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try:
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try:
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coredev = core.Core(comm=comm)
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coredev = core.Core(comm=comm)
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uut = _RTIOSequenceError(
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uut = _RTIOSequenceError(
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@ -5,8 +5,7 @@ from artiq.devices.lda.driver import Lda, Ldasim
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from artiq.language.units import dB
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from artiq.language.units import dB
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no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE")) \
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lda_serial = os.getenv("ARTIQ_LDA_SERIAL")
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or bool(os.getenv("ARTIQ_NO_PERIPHERALS"))
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class GenericLdaTest:
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class GenericLdaTest:
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@ -20,18 +19,11 @@ class GenericLdaTest:
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self.assertEqual(i, self.cont.get_attenuation())
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self.assertEqual(i, self.cont.get_attenuation())
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@unittest.skipIf(no_hardware, "no hardware")
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@unittest.skipUnless(lda_serial, "no hardware")
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class TestLda(GenericLdaTest, unittest.TestCase):
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class TestLda(GenericLdaTest, unittest.TestCase):
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def setUp(self):
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def setUp(self):
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device = os.getenv("ARTIQ_LDA_DEVICE")
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product = os.getenv("ARTIQ_LDA_PRODUCT")
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serial = os.getenv("ARTIQ_LDA_SERIAL")
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self.cont = Lda(serial=lda_serial, product=product)
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args = dict()
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if device is not None:
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args["product"] = device
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if serial is not None:
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args["serial"] = serial
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self.cont = Lda(**args)
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class TestLdaSim(GenericLdaTest, unittest.TestCase):
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class TestLdaSim(GenericLdaTest, unittest.TestCase):
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@ -6,10 +6,6 @@ from artiq.devices.thorlabs_tcube.driver import Tdc, Tpz, TdcSim, TpzSim
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from artiq.language.units import V
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from artiq.language.units import V
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no_hardware = bool(os.getenv("ARTIQ_NO_HARDWARE")) \
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or bool(os.getenv("ARTIQ_NO_PERIPHERALS"))
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class GenericTdcTest:
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class GenericTdcTest:
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def test_pot_parameters(self):
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def test_pot_parameters(self):
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test_vector = 1, 2, 3, 4, 5, 6, 7, 8
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test_vector = 1, 2, 3, 4, 5, 6, 7, 8
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@ -135,11 +131,13 @@ class GenericTpzTest:
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self.assertEqual(test_vector, self.cont.get_tpz_io_settings())
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self.assertEqual(test_vector, self.cont.get_tpz_io_settings())
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@unittest.skipIf(no_hardware, "no hardware")
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tdc_serial = os.getenv("ARTIQ_TDC_SERIAL")
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@unittest.skipUnless(tdc_serial, "no hardware")
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class TestTdc(unittest.TestCase, GenericTdcTest):
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class TestTdc(unittest.TestCase, GenericTdcTest):
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def setUp(self):
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def setUp(self):
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serial_dev = os.getenv("ARTIQ_TDC001_SERIAL", "/dev/ttyUSB0")
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self.cont = Tdc(serial_dev=tdc_serial)
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self.cont = Tdc(serial_dev=serial_dev)
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class TestTdcSim(unittest.TestCase, GenericTdcTest):
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class TestTdcSim(unittest.TestCase, GenericTdcTest):
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self.cont = TdcSim()
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self.cont = TdcSim()
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@unittest.skipIf(no_hardware, "no hardware")
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tpz_serial = os.getenv("ARTIQ_TPZ_SERIAL")
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@unittest.skipUnless(tpz_serial, "no hardware")
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class TestTpz(unittest.TestCase, GenericTpzTest):
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class TestTpz(unittest.TestCase, GenericTpzTest):
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def setUp(self):
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def setUp(self):
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serial_dev = os.getenv("ARTIQ_TPZ001_SERIAL", "/dev/ttyUSB0")
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self.cont = Tpz(serial_dev=tpz_serial)
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self.cont = Tpz(serial_dev=serial_dev)
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class TestTpzSim(unittest.TestCase, GenericTpzTest):
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class TestTpzSim(unittest.TestCase, GenericTpzTest):
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