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ad9912: use pll doubler for refclk <11mhz

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mwojcik 2024-07-15 14:46:00 +08:00 committed by Sébastien Bourdeauducq
parent 86a8d2d87a
commit fb6c1364a6
1 changed files with 10 additions and 2 deletions
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10
artiq/coredevice/ad9912.py
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@ -44,7 +44,11 @@ class AD9912:
self.pll_en = pll_en self.pll_en = pll_en
self.pll_n = pll_n self.pll_n = pll_n
if pll_en: if pll_en:
sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n refclk = self.cpld.refclk
if refclk < 11e6:
# use SYSCLK PLL Doubler
refclk = refclk * 2
sysclk = refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
else: else:
sysclk = self.cpld.refclk sysclk = self.cpld.refclk
assert sysclk <= 1e9 assert sysclk <= 1e9
@ -115,6 +119,10 @@ class AD9912:
self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1) self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1)
self.cpld.io_update.pulse(2 * us) self.cpld.io_update.pulse(2 * us)
# I_cp = 375 µA, VCO high range # I_cp = 375 µA, VCO high range
if self.cpld.refclk < 11e6:
# enable SYSCLK PLL Doubler
self.write(AD9912_PLLCFG, 0b00001101, length=1)
else:
self.write(AD9912_PLLCFG, 0b00000101, length=1) self.write(AD9912_PLLCFG, 0b00000101, length=1)
self.cpld.io_update.pulse(2 * us) self.cpld.io_update.pulse(2 * us)
delay(1 * ms) delay(1 * ms)