occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

wrpll: si549 fixes

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2019-11-20 17:04:24 +08:00
parent c5dbab1929
commit fa41c946ea
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/gateware/drtio/wrpll/si549.py
View File

@ -170,7 +170,7 @@ class ADPLLProgrammer(Module):
self.submodules += master
self.comb += [
master.cg.load.eq(self.i2c_divider.storage),
master.cg.load.eq(self.i2c_divider),
self.scl.eq(master.scl),
master.sda_i.eq(self.sda_i),
self.sda_o.eq(master.sda_o)
@ -184,7 +184,7 @@ class Si549(Module, AutoCSR):
self.gpio_out = CSRStorage(2)
self.gpio_oe = CSRStorage(2)
self.i2c_divider = CSRStorage(16)
self.i2c_divider = CSRStorage(16, reset=2500)
self.i2c_address = CSRStorage(7)
self.errors = CSR(2)
@ -205,7 +205,7 @@ class Si549(Module, AutoCSR):
]
self.comb += [
programmer.adpll.eq(self.adpll),
programmer.adpll_stb.eq(self.adpll_stb)
programmer.stb.eq(self.adpll_stb)
]
self.gpio_enable.storage.attr.add("no_retiming")