forked from M-Labs/artiq
manual: add precision about sequence errors
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@ -126,7 +126,8 @@ Internally, the gateware stores output events in an array of FIFO buffers (the "
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Notes:
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* Strictly increasing timestamps never cause sequence errors.
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* Configuring the gateware with more lanes for the RTIO core reduces the frequency of sequence errors.
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* Configuring the gateware with more lanes for the RTIO core reduces the frequency of sequence errors.
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* The number of lanes is a hard limit on the number of simultaneous RTIO output events.
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* Whether a particular sequence of timestamps causes a sequence error or not is fully deterministic (starting from a known RTIO state, e.g. after a reset). Adding a constant offset to the whole sequence does not affect the result.
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The offending event is discarded and the RTIO core keeps operating.
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