forked from M-Labs/artiq
siphaser: fix phase_shift_done CSR
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acfd9db185
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f7aba6b570
@ -10,7 +10,7 @@ class SiPhaser7Series(Module, AutoCSR):
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def __init__(self, si5324_clkin, si5324_clkout_fabric):
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def __init__(self, si5324_clkin, si5324_clkout_fabric):
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self.switch_clocks = CSRStorage()
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self.switch_clocks = CSRStorage()
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self.phase_shift = CSR()
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus()
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self.phase_shift_done = CSRStatus(reset=1)
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self.sample_result = CSRStatus()
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self.sample_result = CSRStatus()
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# 125MHz system clock to 150MHz. VCO @ 625MHz.
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# 125MHz system clock to 150MHz. VCO @ 625MHz.
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@ -37,6 +37,7 @@ class SiPhaser7Series(Module, AutoCSR):
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# non-determinstic skew of Si5324.
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# non-determinstic skew of Si5324.
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mmcm_ps_fb = Signal()
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mmcm_ps_fb = Signal()
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mmcm_ps_output = Signal()
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mmcm_ps_output = Signal()
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mmcm_ps_psdone = Signal()
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self.specials += \
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self.specials += \
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Instance("MMCME2_ADV",
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Instance("MMCME2_ADV",
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p_CLKIN1_PERIOD=1e9/150e6,
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p_CLKIN1_PERIOD=1e9/150e6,
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@ -56,8 +57,12 @@ class SiPhaser7Series(Module, AutoCSR):
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i_PSCLK=ClockSignal(),
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i_PSCLK=ClockSignal(),
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i_PSEN=self.phase_shift.re,
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i_PSEN=self.phase_shift.re,
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i_PSINCDEC=self.phase_shift.r,
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i_PSINCDEC=self.phase_shift.r,
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o_PSDONE=self.phase_shift_done.status,
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o_PSDONE=mmcm_ps_psdone,
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)
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)
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self.sync += [
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If(self.phase_shift.re, self.phase_shift_done.status.eq(0)),
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If(mmcm_ps_psdone, self.phase_shift_done.status.eq(1))
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]
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si5324_clkin_se = Signal()
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si5324_clkin_se = Signal()
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self.specials += [
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self.specials += [
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