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gateware: make 7-series EEM handling functions shareable

This commit is contained in:
Sebastien Bourdeauducq 2021-02-07 14:34:26 +08:00
parent 1213f78ee9
commit f7a33a1f99
2 changed files with 132 additions and 130 deletions

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@ -0,0 +1,127 @@
from artiq.gateware import eem
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
def peripheral_dio(module, peripheral):
ttl_classes = {
"input": ttl_serdes_7series.InOut_8X,
"output": ttl_serdes_7series.Output_8X
}
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
if peripheral["edge_counter"]:
edge_counter_cls = edge_counter.SimpleEdgeCounter
else:
edge_counter_cls = None
eem.DIO.add_std(module, peripheral["ports"][0],
ttl_classes[peripheral["bank_direction_low"]],
ttl_classes[peripheral["bank_direction_high"]],
edge_counter_cls=edge_counter_cls)
def peripheral_urukul(module, peripheral):
if len(peripheral["ports"]) == 1:
port, port_aux = peripheral["ports"][0], None
elif len(peripheral["ports"]) == 2:
port, port_aux = peripheral["ports"]
else:
raise ValueError("wrong number of ports")
if peripheral["synchronization"]:
sync_gen_cls = ttl_simple.ClockGen
else:
sync_gen_cls = None
eem.Urukul.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
sync_gen_cls)
def peripheral_novogorny(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Novogorny.add_std(module, peripheral["ports"][0], ttl_serdes_7series.Output_8X)
def peripheral_sampler(module, peripheral):
if len(peripheral["ports"]) == 1:
port, port_aux = peripheral["ports"][0], None
elif len(peripheral["ports"]) == 2:
port, port_aux = peripheral["ports"]
else:
raise ValueError("wrong number of ports")
eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X)
def peripheral_suservo(module, peripheral):
if len(peripheral["sampler_ports"]) != 2:
raise ValueError("wrong number of Sampler ports")
urukul_ports = []
if len(peripheral["urukul0_ports"]) != 2:
raise ValueError("wrong number of Urukul #0 ports")
urukul_ports.append(peripheral["urukul0_ports"])
if "urukul1_ports" in peripheral:
if len(peripheral["urukul1_ports"]) != 2:
raise ValueError("wrong number of Urukul #1 ports")
urukul_ports.append(peripheral["urukul1_ports"])
eem.SUServo.add_std(module,
peripheral["sampler_ports"],
urukul_ports)
def peripheral_zotino(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Zotino.add_std(module, peripheral["ports"][0],
ttl_serdes_7series.Output_8X)
def peripheral_grabber(module, peripheral):
if len(peripheral["ports"]) == 1:
port = peripheral["ports"][0]
port_aux = None
port_aux2 = None
elif len(peripheral["ports"]) == 2:
port, port_aux = peripheral["ports"]
port_aux2 = None
elif len(peripheral["ports"]) == 3:
port, port_aux, port_aux2 = peripheral["ports"]
else:
raise ValueError("wrong number of ports")
eem.Grabber.add_std(module, port, port_aux, port_aux2)
def peripheral_mirny(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Mirny.add_std(module, peripheral["ports"][0],
ttl_serdes_7series.Output_8X)
def peripheral_fastino(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Fastino.add_std(module, peripheral["ports"][0],
peripheral["log2_width"])
def peripheral_phaser(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Phaser.add_std(module, peripheral["ports"][0])
peripheral_processors = {
"dio": peripheral_dio,
"urukul": peripheral_urukul,
"novogorny": peripheral_novogorny,
"sampler": peripheral_sampler,
"suservo": peripheral_suservo,
"zotino": peripheral_zotino,
"grabber": peripheral_grabber,
"mirny": peripheral_mirny,
"fastino": peripheral_fastino,
"phaser": peripheral_phaser,
}
def add_peripherals(module, peripherals):
for peripheral in peripherals:
peripheral_processors[peripheral["type"]](module, peripheral)

View File

@ -6,137 +6,12 @@ from misoc.integration.builder import builder_args, builder_argdict
from misoc.targets.kasli import soc_kasli_args, soc_kasli_argdict from misoc.targets.kasli import soc_kasli_args, soc_kasli_argdict
from artiq.coredevice import jsondesc from artiq.coredevice import jsondesc
from artiq.gateware import rtio, eem from artiq.gateware import rtio, eem_7series
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.targets.kasli import StandaloneBase, MasterBase, SatelliteBase from artiq.gateware.targets.kasli import StandaloneBase, MasterBase, SatelliteBase
from artiq.build_soc import * from artiq.build_soc import *
def peripheral_dio(module, peripheral):
ttl_classes = {
"input": ttl_serdes_7series.InOut_8X,
"output": ttl_serdes_7series.Output_8X
}
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
if peripheral["edge_counter"]:
edge_counter_cls = edge_counter.SimpleEdgeCounter
else:
edge_counter_cls = None
eem.DIO.add_std(module, peripheral["ports"][0],
ttl_classes[peripheral["bank_direction_low"]],
ttl_classes[peripheral["bank_direction_high"]],
edge_counter_cls=edge_counter_cls)
def peripheral_urukul(module, peripheral):
if len(peripheral["ports"]) == 1:
port, port_aux = peripheral["ports"][0], None
elif len(peripheral["ports"]) == 2:
port, port_aux = peripheral["ports"]
else:
raise ValueError("wrong number of ports")
if peripheral["synchronization"]:
sync_gen_cls = ttl_simple.ClockGen
else:
sync_gen_cls = None
eem.Urukul.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
sync_gen_cls)
def peripheral_novogorny(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Novogorny.add_std(module, peripheral["ports"][0], ttl_serdes_7series.Output_8X)
def peripheral_sampler(module, peripheral):
if len(peripheral["ports"]) == 1:
port, port_aux = peripheral["ports"][0], None
elif len(peripheral["ports"]) == 2:
port, port_aux = peripheral["ports"]
else:
raise ValueError("wrong number of ports")
eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X)
def peripheral_suservo(module, peripheral):
if len(peripheral["sampler_ports"]) != 2:
raise ValueError("wrong number of Sampler ports")
urukul_ports = []
if len(peripheral["urukul0_ports"]) != 2:
raise ValueError("wrong number of Urukul #0 ports")
urukul_ports.append(peripheral["urukul0_ports"])
if "urukul1_ports" in peripheral:
if len(peripheral["urukul1_ports"]) != 2:
raise ValueError("wrong number of Urukul #1 ports")
urukul_ports.append(peripheral["urukul1_ports"])
eem.SUServo.add_std(module,
peripheral["sampler_ports"],
urukul_ports)
def peripheral_zotino(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Zotino.add_std(module, peripheral["ports"][0],
ttl_serdes_7series.Output_8X)
def peripheral_grabber(module, peripheral):
if len(peripheral["ports"]) == 1:
port = peripheral["ports"][0]
port_aux = None
port_aux2 = None
elif len(peripheral["ports"]) == 2:
port, port_aux = peripheral["ports"]
port_aux2 = None
elif len(peripheral["ports"]) == 3:
port, port_aux, port_aux2 = peripheral["ports"]
else:
raise ValueError("wrong number of ports")
eem.Grabber.add_std(module, port, port_aux, port_aux2)
def peripheral_mirny(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Mirny.add_std(module, peripheral["ports"][0],
ttl_serdes_7series.Output_8X)
def peripheral_fastino(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Fastino.add_std(module, peripheral["ports"][0],
peripheral["log2_width"])
def peripheral_phaser(module, peripheral):
if len(peripheral["ports"]) != 1:
raise ValueError("wrong number of ports")
eem.Phaser.add_std(module, peripheral["ports"][0])
peripheral_processors = {
"dio": peripheral_dio,
"urukul": peripheral_urukul,
"novogorny": peripheral_novogorny,
"sampler": peripheral_sampler,
"suservo": peripheral_suservo,
"zotino": peripheral_zotino,
"grabber": peripheral_grabber,
"mirny": peripheral_mirny,
"fastino": peripheral_fastino,
"phaser": peripheral_phaser,
}
def add_peripherals(module, peripherals):
for peripheral in peripherals:
peripheral_processors[peripheral["type"]](module, peripheral)
class GenericStandalone(StandaloneBase): class GenericStandalone(StandaloneBase):
def __init__(self, description, hw_rev=None,**kwargs): def __init__(self, description, hw_rev=None,**kwargs):
if hw_rev is None: if hw_rev is None:
@ -159,7 +34,7 @@ class GenericStandalone(StandaloneBase):
self.grabber_csr_group = [] self.grabber_csr_group = []
self.rtio_channels = [] self.rtio_channels = []
add_peripherals(self, description["peripherals"]) eem_7series.add_peripherals(self, description["peripherals"])
if hw_rev in ("v1.0", "v1.1"): if hw_rev in ("v1.0", "v1.1"):
for i in (1, 2): for i in (1, 2):
print("SFP LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels))) print("SFP LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
@ -204,7 +79,7 @@ class GenericMaster(MasterBase):
self.grabber_csr_group = [] self.grabber_csr_group = []
self.rtio_channels = [] self.rtio_channels = []
add_peripherals(self, description["peripherals"]) eem_7series.add_peripherals(self, description["peripherals"])
self.config["HAS_RTIO_LOG"] = None self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel()) self.rtio_channels.append(rtio.LogChannel())
@ -237,7 +112,7 @@ class GenericSatellite(SatelliteBase):
self.grabber_csr_group = [] self.grabber_csr_group = []
self.rtio_channels = [] self.rtio_channels = []
add_peripherals(self, description["peripherals"]) eem_7series.add_peripherals(self, description["peripherals"])
self.config["HAS_RTIO_LOG"] = None self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
self.rtio_channels.append(rtio.LogChannel()) self.rtio_channels.append(rtio.LogChannel())