forked from M-Labs/artiq
drtio: fix ad9154 extension registration
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parent
3aced46b19
commit
f6024b6c9a
@ -53,7 +53,7 @@ class Master(MiniSoC, AMPSoC):
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elif cfg == "sawg_3g":
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elif cfg == "sawg_3g":
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# 3Gb link, 150MHz RTIO clock
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# 3Gb link, 150MHz RTIO clock
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# with SAWG on local RTIO and AD9154-FMC-EBZ
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# with SAWG on local RTIO and AD9154-FMC-EBZ
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platform.register_extension(ad9154_fmc_ebz)
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platform.add_extension(ad9154_fmc_ebz)
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self.submodules.transceiver = gtx_7series.GTX_3G(
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self.submodules.transceiver = gtx_7series.GTX_3G(
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clock_pads=platform.request("ad9154_refclk"),
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clock_pads=platform.request("ad9154_refclk"),
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tx_pads=tx_pads,
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tx_pads=tx_pads,
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@ -169,7 +169,7 @@ class Satellite(BaseSoC):
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elif cfg == "sawg_3g":
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elif cfg == "sawg_3g":
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# 3Gb link, 150MHz RTIO clock
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# 3Gb link, 150MHz RTIO clock
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# with SAWG on local RTIO and AD9154-FMC-EBZ
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# with SAWG on local RTIO and AD9154-FMC-EBZ
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platform.register_extension(ad9154_fmc_ebz)
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platform.add_extension(ad9154_fmc_ebz)
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self.submodules.transceiver = gtx_7series.GTX_3G(
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self.submodules.transceiver = gtx_7series.GTX_3G(
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clock_pads=platform.request("ad9154_refclk"),
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clock_pads=platform.request("ad9154_refclk"),
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tx_pads=tx_pads,
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tx_pads=tx_pads,
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