forked from M-Labs/artiq
serwb/core: reduce buffering, use buffered=True
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@ -17,8 +17,8 @@ class SERWBCore(Module):
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self.submodules += depacketizer, packetizer
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# fifos
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tx_fifo = stream.SyncFIFO([("data", 32)], 16)
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rx_fifo = stream.SyncFIFO([("data", 32)], 16)
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tx_fifo = stream.SyncFIFO([("data", 32)], 8, buffered=True)
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rx_fifo = stream.SyncFIFO([("data", 32)], 8, buffered=True)
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self.submodules += tx_fifo, rx_fifo
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# modules connection
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