occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

serwb/core: reduce buffering, use buffered=True

Browse Source
This commit is contained in:
Florent Kermarrec 2018-05-12 12:03:58 +02:00
parent fdc953e569
commit f5208ff2f3
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/serwb/core.py
View File

@ -17,8 +17,8 @@ class SERWBCore(Module):
self.submodules += depacketizer, packetizer self.submodules += depacketizer, packetizer
# fifos # fifos
tx_fifo = stream.SyncFIFO([("data", 32)], 16) tx_fifo = stream.SyncFIFO([("data", 32)], 8, buffered=True)
rx_fifo = stream.SyncFIFO([("data", 32)], 16) rx_fifo = stream.SyncFIFO([("data", 32)], 8, buffered=True)
self.submodules += tx_fifo, rx_fifo self.submodules += tx_fifo, rx_fifo
# modules connection # modules connection