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urukul: don't pulse DDS_RST on init 

closes m-labs/artiq#940

Apparently, if the DDS are reset, every other time they don't work
properly.
This commit is contained in:
Robert Jördens 2018-03-20 16:10:26 +00:00
parent a185e8dc52
commit f17c0abfe4
1 changed files with 1 additions and 1 deletions
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artiq/coredevice/urukul.py
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@ -169,7 +169,7 @@ class CPLD:
Resets the DDS and verifies correct CPLD gateware version. Resets the DDS and verifies correct CPLD gateware version.
""" """
cfg = self.cfg_reg cfg = self.cfg_reg
self.cfg_reg = cfg | (1 << CFG_RST) | (1 << CFG_IO_RST) self.cfg_reg = cfg | (0 << CFG_RST) | (1 << CFG_IO_RST)
proto_rev = urukul_sta_proto_rev(self.sta_read()) proto_rev = urukul_sta_proto_rev(self.sta_read())
if proto_rev != STA_PROTO_REV_MATCH: if proto_rev != STA_PROTO_REV_MATCH:
raise ValueError("Urukul proto_rev mismatch") raise ValueError("Urukul proto_rev mismatch")