forked from M-Labs/artiq
Merge branch 'master' into new-py2llvm
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commit
ef4a06a270
@ -15,7 +15,7 @@ done
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for a in $archives
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for a in $archives
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do
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do
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wget $a
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wget $a
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(cd packages && tar xvf ../$(basename $a))
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(cd packages && tar xf ../$(basename $a))
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done
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done
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export PATH=$PWD/packages/usr/local/llvm-or1k/bin:$PWD/packages/usr/local/bin:$PWD/packages/usr/bin:$PATH
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export PATH=$PWD/packages/usr/local/llvm-or1k/bin:$PWD/packages/usr/local/bin:$PWD/packages/usr/bin:$PATH
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@ -50,7 +50,7 @@ NET "{int_clk}" TNM_NET = "GRPint_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSfix_ise1" = FROM "GRPint_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise1" = FROM "GRPint_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
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TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
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""", int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
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""", int_clk=rtio_internal_clk)
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class NIST_QC1(BaseSoC, AMPSoC):
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class NIST_QC1(BaseSoC, AMPSoC):
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