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rtio: remove support for async mode

This commit is contained in:
Sebastien Bourdeauducq 2023-01-06 18:22:05 +08:00
parent 573a895c1e
commit ec893222a4
14 changed files with 53 additions and 107 deletions
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4
artiq/gateware/drtio/core.py
View File

@ -58,7 +58,7 @@ class SyncRTIO(Module):
assert tsc.glbl_fine_ts_width >= chan_fine_ts_width
self.submodules.outputs = ClockDomainsRenamer("rio")(
SED(channels, tsc.glbl_fine_ts_width, "sync",
SED(channels, tsc.glbl_fine_ts_width,
lane_count=lane_count, fifo_depth=fifo_depth,
enable_spread=False, report_buffer_space=True,
interface=self.cri))
@ -66,7 +66,7 @@ class SyncRTIO(Module):
self.sync += self.outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 16)
self.submodules.inputs = ClockDomainsRenamer("rio")(
InputCollector(tsc, channels, "sync", interface=self.cri))
InputCollector(tsc, channels, interface=self.cri))
for attr, _ in async_errors_layout:
self.comb += getattr(self.async_errors, attr).eq(getattr(self.outputs, attr))

4
artiq/gateware/rtio/core.py
View File

@ -60,7 +60,7 @@ class Core(Module, AutoCSR):
# Outputs/Inputs
quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)]
outputs = SED(channels, tsc.glbl_fine_ts_width, "sync",
outputs = SED(channels, tsc.glbl_fine_ts_width,
quash_channels=quash_channels,
lane_count=lane_count, fifo_depth=fifo_depth,
interface=self.cri)
@ -68,7 +68,7 @@ class Core(Module, AutoCSR):
self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts)
self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts + 16)
inputs = InputCollector(tsc, channels, "sync",
inputs = InputCollector(tsc, channels,
quash_channels=quash_channels,
interface=self.cri)
self.submodules += inputs

22
artiq/gateware/rtio/cri.py
View File

@ -127,7 +127,7 @@ class KernelInitiator(Module, AutoCSR):
class CRIDecoder(Module):
def __init__(self, slaves=2, master=None, mode="async", enable_routing=False):
def __init__(self, slaves=2, master=None, enable_routing=False):
if isinstance(slaves, int):
slaves = [Interface() for _ in range(slaves)]
if master is None:
@ -155,10 +155,7 @@ class CRIDecoder(Module):
if enable_routing:
self.specials.routing_table = Memory(slave_bits, 256)
if mode == "async" or mode == "sync":
rtp_decoder = self.routing_table.get_port()
else:
raise ValueError
rtp_decoder = self.routing_table.get_port()
self.specials += rtp_decoder
self.comb += [
rtp_decoder.adr.eq(self.master.chan_sel[16:]),
@ -185,7 +182,7 @@ class CRIDecoder(Module):
class CRISwitch(Module, AutoCSR):
def __init__(self, masters=2, slave=None, mode="async"):
def __init__(self, masters=2, slave=None):
if isinstance(masters, int):
masters = [Interface() for _ in range(masters)]
if slave is None:
@ -197,11 +194,6 @@ class CRISwitch(Module, AutoCSR):
# # #
if mode == "async" or mode == "sync":
selected = self.selected.storage
else:
raise ValueError
if len(masters) == 1:
self.comb += masters[0].connect(slave)
else:
@ -209,7 +201,7 @@ class CRISwitch(Module, AutoCSR):
for name, size, direction in layout:
if direction == DIR_M_TO_S:
choices = Array(getattr(m, name) for m in masters)
self.comb += getattr(slave, name).eq(choices[selected])
self.comb += getattr(slave, name).eq(choices[self.selected.storage])
# connect slave->master signals
for name, size, direction in layout:
@ -221,10 +213,10 @@ class CRISwitch(Module, AutoCSR):
class CRIInterconnectShared(Module):
def __init__(self, masters=2, slaves=2, mode="async", enable_routing=False):
def __init__(self, masters=2, slaves=2, enable_routing=False):
shared = Interface()
self.submodules.switch = CRISwitch(masters, shared, mode)
self.submodules.decoder = CRIDecoder(slaves, shared, mode, enable_routing)
self.submodules.switch = CRISwitch(masters, shared)
self.submodules.decoder = CRIDecoder(slaves, shared, enable_routing)
def get_csrs(self):
return self.switch.get_csrs()

36
artiq/gateware/rtio/input_collector.py
View File

@ -1,6 +1,6 @@
from migen import *
from migen.genlib.record import Record
from migen.genlib.fifo import *
from migen.genlib.fifo import SyncFIFOBuffered
from migen.genlib.cdc import BlindTransfer
from artiq.gateware.rtio import cri
@ -24,24 +24,13 @@ def get_channel_layout(coarse_ts_width, interface):
class InputCollector(Module):
def __init__(self, tsc, channels, mode, quash_channels=[], interface=None):
def __init__(self, tsc, channels, quash_channels=[], interface=None):
if interface is None:
interface = cri.Interface()
self.cri = interface
# # #
if mode == "sync":
fifo_factory = SyncFIFOBuffered
sync_io = self.sync
sync_cri = self.sync
elif mode == "async":
fifo_factory = lambda *args: ClockDomainsRenamer({"write": "rio", "read": "sys"})(AsyncFIFO(*args))
sync_io = self.sync.rio
sync_cri = self.sync.sys
else:
raise ValueError
i_statuses, i_datas, i_timestamps = [], [], []
i_ack = Signal()
sel = self.cri.chan_sel[:16]
@ -55,7 +44,7 @@ class InputCollector(Module):
# FIFO
layout = get_channel_layout(len(tsc.coarse_ts), iif)
fifo = fifo_factory(layout_len(layout), channel.ififo_depth)
fifo = SyncFIFOBuffered(layout_len(layout), channel.ififo_depth)
self.submodules += fifo
fifo_in = Record(layout)
fifo_out = Record(layout)
@ -67,7 +56,7 @@ class InputCollector(Module):
# FIFO write
if iif.delay:
counter_rtio = Signal.like(tsc.coarse_ts, reset_less=True)
sync_io += counter_rtio.eq(tsc.coarse_ts - (iif.delay + 1))
self.sync += counter_rtio.eq(tsc.coarse_ts - (iif.delay + 1))
else:
counter_rtio = tsc.coarse_ts
if hasattr(fifo_in, "data"):
@ -80,17 +69,8 @@ class InputCollector(Module):
self.comb += fifo_in.timestamp.eq(full_ts)
self.comb += fifo.we.eq(iif.stb)
overflow_io = Signal()
self.comb += overflow_io.eq(fifo.we & ~fifo.writable)
if mode == "sync":
overflow_trigger = overflow_io
elif mode == "async":
overflow_transfer = BlindTransfer("rio", "sys")
self.submodules += overflow_transfer
self.comb += overflow_transfer.i.eq(overflow_io)
overflow_trigger = overflow_transfer.o
else:
raise ValueError
overflow_trigger = Signal()
self.comb += overflow_trigger.eq(fifo.we & ~fifo.writable)
# FIFO read, CRI connection
if hasattr(fifo_out, "data"):
@ -107,7 +87,7 @@ class InputCollector(Module):
self.comb += selected.eq(sel == n)
overflow = Signal()
sync_cri += [
self.sync += [
If(selected & i_ack,
overflow.eq(0)),
If(overflow_trigger,
@ -122,7 +102,7 @@ class InputCollector(Module):
input_pending = Signal()
self.cri.i_data.reset_less = True
self.cri.i_timestamp.reset_less = True
sync_cri += [
self.sync += [
i_ack.eq(0),
If(i_ack,
self.cri.i_status.eq(Cat(~i_status_raw[0], i_status_raw[1], 0)),

46
artiq/gateware/rtio/sed/core.py
View File

@ -11,41 +11,25 @@ __all__ = ["SED"]
class SED(Module):
def __init__(self, channels, glbl_fine_ts_width, mode,
def __init__(self, channels, glbl_fine_ts_width,
lane_count=8, fifo_depth=128, enable_spread=True,
quash_channels=[], report_buffer_space=False, interface=None):
if mode == "sync":
lane_dist_cdr = lambda x: x
fifos_cdr = lambda x: x
gates_cdr = lambda x: x
output_driver_cdr = lambda x: x
elif mode == "async":
lane_dist_cdr = ClockDomainsRenamer("sys")
fifos_cdr = ClockDomainsRenamer({"write": "sys", "read": "rio"})
gates_cdr = ClockDomainsRenamer("rio")
output_driver_cdr = ClockDomainsRenamer("rio")
else:
raise ValueError
seqn_width = layouts.seqn_width(lane_count, fifo_depth)
self.submodules.lane_dist = lane_dist_cdr(
LaneDistributor(lane_count, seqn_width,
layouts.fifo_payload(channels),
[channel.interface.o.delay for channel in channels],
glbl_fine_ts_width,
enable_spread=enable_spread,
quash_channels=quash_channels,
interface=interface))
self.submodules.fifos = fifos_cdr(
FIFOs(lane_count, fifo_depth,
layouts.fifo_payload(channels), mode, report_buffer_space))
self.submodules.gates = gates_cdr(
Gates(lane_count, seqn_width,
layouts.fifo_payload(channels),
layouts.output_network_payload(channels, glbl_fine_ts_width)))
self.submodules.output_driver = output_driver_cdr(
OutputDriver(channels, glbl_fine_ts_width, lane_count, seqn_width))
self.submodules.lane_dist = LaneDistributor(lane_count, seqn_width,
layouts.fifo_payload(channels),
[channel.interface.o.delay for channel in channels],
glbl_fine_ts_width,
enable_spread=enable_spread,
quash_channels=quash_channels,
interface=interface)
self.submodules.fifos = FIFOs(lane_count, fifo_depth,
layouts.fifo_payload(channels), report_buffer_space)
self.submodules.gates = Gates(lane_count, seqn_width,
layouts.fifo_payload(channels),
layouts.output_network_payload(channels, glbl_fine_ts_width))
self.submodules.output_driver = OutputDriver(channels, glbl_fine_ts_width,
lane_count, seqn_width)
for o, i in zip(self.lane_dist.output, self.fifos.input):
self.comb += o.connect(i)

16
artiq/gateware/rtio/sed/fifos.py
View File

@ -2,7 +2,7 @@ from operator import or_
from functools import reduce
from migen import *
from migen.genlib.fifo import *
from migen.genlib.fifo import SyncFIFOBuffered
from artiq.gateware.rtio.sed import layouts
@ -11,7 +11,7 @@ __all__ = ["FIFOs"]
class FIFOs(Module):
def __init__(self, lane_count, fifo_depth, layout_payload, mode, report_buffer_space=False):
def __init__(self, lane_count, fifo_depth, layout_payload, report_buffer_space=False):
seqn_width = layouts.seqn_width(lane_count, fifo_depth)
self.input = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
for _ in range(lane_count)]
@ -23,16 +23,9 @@ class FIFOs(Module):
# # #
if mode == "sync":
fifo_cls = SyncFIFOBuffered
elif mode == "async":
fifo_cls = AsyncFIFOBuffered
else:
raise ValueError
fifos = []
for input, output in zip(self.input, self.output):
fifo = fifo_cls(seqn_width + layout_len(layout_payload), fifo_depth)
fifo = SyncFIFOBuffered(seqn_width + layout_len(layout_payload), fifo_depth)
self.submodules += fifo
fifos.append(fifo)
@ -47,9 +40,6 @@ class FIFOs(Module):
]
if report_buffer_space:
if mode != "sync":
raise NotImplementedError
def compute_max(elts):
l = len(elts)
if l == 1:

2
artiq/gateware/rtio/tsc.py
View File

@ -1,7 +1,7 @@
from migen import *
class TSC(Module):
def __init__(self, mode, glbl_fine_ts_width=0):
def __init__(self, glbl_fine_ts_width=0):
self.glbl_fine_ts_width = glbl_fine_ts_width
# in rtio domain

8
artiq/gateware/targets/kasli.py
View File

@ -102,7 +102,7 @@ class StandaloneBase(MiniSoC, AMPSoC):
def add_rtio(self, rtio_channels, sed_lanes=8):
fix_serdes_timing_path(self.platform)
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
@ -286,7 +286,7 @@ class MasterBase(MiniSoC, AMPSoC):
self.comb += [self.virtual_leds.get(i + 1).eq(channel.rx_ready)
for i, channel in enumerate(sfp_channels)]
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
@ -480,7 +480,7 @@ class SatelliteBase(BaseSoC):
self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
for i, channel in enumerate(sfp_channels)]
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
@ -573,7 +573,7 @@ class SatelliteBase(BaseSoC):
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True)
enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")

8
artiq/gateware/targets/kc705.py
View File

@ -149,7 +149,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
self.config["HAS_DDS"] = None
def add_rtio(self, rtio_channels):
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
@ -218,7 +218,7 @@ class _MasterBase(MiniSoC, AMPSoC):
clk_freq=self.clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
@ -358,7 +358,7 @@ class _SatelliteBase(BaseSoC):
clk_freq=self.clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
@ -456,7 +456,7 @@ class _SatelliteBase(BaseSoC):
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True)
enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")

2
artiq/gateware/test/drtio/test_full_stack.py
View File

@ -67,7 +67,7 @@ class DUT(Module):
rtio.Channel.from_phy(self.phy1),
rtio.Channel.from_phy(self.phy2),
]
self.submodules.tsc_satellite = rtio.TSC("sync")
self.submodules.tsc_satellite = rtio.TSC()
self.submodules.satellite = DRTIOSatellite(
self.tsc_satellite, self.transceivers.bob, rx_synchronizer)
self.satellite.reset.storage.reset = 0

4
artiq/gateware/test/drtio/test_switching.py
View File

@ -40,12 +40,12 @@ class DUT(Module):
def __init__(self, nwords):
self.transceivers = DummyTransceiverPair(nwords)
self.submodules.tsc_master = rtio.TSC("async")
self.submodules.tsc_master = rtio.TSC()
self.submodules.master = DRTIOMaster(self.tsc_master,
self.transceivers.alice)
rx_synchronizer = DummyRXSynchronizer()
self.submodules.tsc_satellite = rtio.TSC("sync")
self.submodules.tsc_satellite = rtio.TSC()
self.submodules.satellite = DRTIOSatellite(
self.tsc_satellite, self.transceivers.bob, rx_synchronizer)
self.satellite.reset.storage.reset = 0

2
artiq/gateware/test/rtio/test_dma.py
View File

@ -128,7 +128,7 @@ class FullStackTB(Module):
self.submodules.memory = wishbone.SRAM(
256, init=sequence, bus=bus)
self.submodules.dut = dma.DMA(bus, dw)
self.submodules.tsc = rtio.TSC("async")
self.submodules.tsc = rtio.TSC()
self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
self.comb += self.dut.cri.connect(self.rtio.cri)

4
artiq/gateware/test/rtio/test_input_collector.py
View File

@ -38,8 +38,8 @@ class DUT(Module):
rtio.Channel.from_phy(self.phy0, ififo_depth=4),
rtio.Channel.from_phy(self.phy1, ififo_depth=4)
]
self.submodules.tsc = ClockDomainsRenamer({"rtio": "sys"})(rtio.TSC("sync"))
self.submodules.input_collector = InputCollector(self.tsc, rtio_channels, "sync")
self.submodules.tsc = rtio.TSC()
self.submodules.input_collector = InputCollector(self.tsc, rtio_channels)
@property
def cri(self):

2
artiq/gateware/test/rtio/test_sed_top.py
View File

@ -22,7 +22,7 @@ class DUT(Module):
rtio.Channel.from_phy(self.phy1)
]
self.submodules.sed = SED(rtio_channels, 0, "sync", **kwargs)
self.submodules.sed = SED(rtio_channels, 0, **kwargs)
self.sync += [
self.sed.coarse_timestamp.eq(self.sed.coarse_timestamp + 1),
self.sed.minimum_coarse_timestamp.eq(self.sed.coarse_timestamp + 16)