forked from M-Labs/artiq
gateware: remove SAWG simulations
This commit is contained in:
parent
cee9f3f44e
commit
ea21f474a7
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@ -1,112 +0,0 @@
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import numpy as np
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import matplotlib.pyplot as plt
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from migen import *
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from migen.fhdl import verilog
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from artiq.gateware.dsp import fir
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class Transfer(Module):
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def __init__(self, dut):
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self.submodules.dut = dut
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def drive(self, x):
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for xi in x.reshape(-1, self.dut.parallelism):
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yield [ij.eq(int(xj)) for ij, xj in zip(self.dut.i, xi)]
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yield
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def record(self, y):
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for i in range(self.dut.latency):
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yield
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for yi in y.reshape(-1, self.dut.parallelism):
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yield
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yi[:] = (yield from [(yield o) for o in self.dut.o])
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def run(self, samples, amplitude=1., seed=None):
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if seed is not None:
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np.random.seed(seed)
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w = 2**(self.dut.width - 1) - 1
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x = np.round(np.random.uniform(
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-amplitude*w, amplitude*w, samples))
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y = self.run_data(x)
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x /= w
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y /= w
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return x, y
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def run_data(self, x):
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y = np.empty_like(x)
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run_simulation(self, [self.drive(x), self.record(y)],
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vcd_name="fir.vcd")
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return y
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def analyze(self, x, y):
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fig, ax = plt.subplots(3)
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ax[0].plot(x, "c-.", label="input")
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ax[0].plot(y, "r-", label="output")
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ax[0].legend(loc="right")
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ax[0].set_xlabel("time (1/fs)")
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ax[0].set_ylabel("signal")
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n = len(x)
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w = np.hanning(n)
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x = (x.reshape(-1, n)*w).sum(0)
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y = (y.reshape(-1, n)*w).sum(0)
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t = (np.fft.rfft(y)/np.fft.rfft(x))
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f = np.fft.rfftfreq(n)*2
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fmin = f[1]
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ax[1].plot(f, 20*np.log10(np.abs(t)), "r-")
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ax[1].set_ylim(-70, 3)
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ax[1].set_xlim(fmin, 1.)
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# ax[1].set_xscale("log")
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ax[1].set_xlabel("frequency (fs/2)")
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ax[1].set_ylabel("magnitude (dB)")
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ax[1].grid(True)
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ax[2].plot(f, np.rad2deg(np.angle(t)), "r-")
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ax[2].set_xlim(fmin, 1.)
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# ax[2].set_xscale("log")
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ax[2].set_xlabel("frequency (fs/2)")
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ax[2].set_ylabel("phase (deg)")
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ax[2].grid(True)
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return fig
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class UpTransfer(Transfer):
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def drive(self, x):
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x = x.reshape(-1, len(self.dut.o))
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x[:, 1:] = 0
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for xi in x:
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yield self.dut.i.eq(int(xi[0]))
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yield
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def record(self, y):
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for i in range(self.dut.latency):
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yield
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for yi in y.reshape(-1, len(self.dut.o)):
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yield
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yi[:] = (yield from [(yield o) for o in self.dut.o])
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def _main():
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if True:
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coeff = fir.halfgen4_cascade(2, width=.4, order=8)
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dut = fir.ParallelHBFUpsampler(coeff, width=16)
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# print(verilog.convert(dut, ios=set([dut.i] + dut.o)))
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tb = UpTransfer(dut)
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else:
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coeff = fir.halfgen4(.4/2, 8)
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dut = fir.ParallelFIR(coeff, parallelism=4, width=16)
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# print(verilog.convert(dut, ios=set(dut.i + dut.o)))
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tb = Transfer(dut)
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if True:
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x, y = tb.run(samples=1 << 10, amplitude=.5, seed=0x1234567)
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else:
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x = np.zeros(100)
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x[:50] = 1 << 8
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x[50:] = 1 << 13
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y = tb.run_data(x)
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tb.analyze(x, y)
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plt.show()
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if __name__ == "__main__":
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_main()
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@ -1,46 +0,0 @@
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import numpy as np
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from migen import *
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp.accu import Accu, PhasedAccu
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from .tools import xfer
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def read(o, n):
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p = []
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for i in range(n):
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p.append((yield from [(yield pi) for pi in o.payload.flatten()]))
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yield
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return p
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def _test_gen_accu(dut, o):
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yield dut.o.ack.eq(1)
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yield from xfer(dut, i=dict(p=0, f=1, clr=1))
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o.extend((yield from read(dut.o, 8)))
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yield from xfer(dut, i=dict(p=0, f=2, clr=0))
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o.extend((yield from read(dut.o, 8)))
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yield from xfer(dut, i=dict(p=0, f=2, clr=1))
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o.extend((yield from read(dut.o, 8)))
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yield from xfer(dut, i=dict(p=8, f=-1, clr=1))
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o.extend((yield from read(dut.o, 8)))
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yield from xfer(dut, i=dict(p=0, f=0, clr=1))
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yield from xfer(dut, i=dict(p=1, f=0, clr=0))
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o.extend((yield from read(dut.o, 8)))
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def _test_accu():
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dut = PhasedAccu(8, parallelism=8)
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if False:
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print(convert(dut))
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else:
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o = []
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run_simulation(dut, _test_gen_accu(dut, o), vcd_name="accu.vcd")
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o = np.array(o)
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print(o)
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if __name__ == "__main__":
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_test_accu()
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@ -1,71 +0,0 @@
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import unittest
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import migen as mg
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from artiq.gateware.dsp.tools import SatAddMixin
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class DUT(mg.Module, SatAddMixin):
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def __init__(self, width):
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self.o = mg.Signal((width, True))
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self.i0 = mg.Signal.like(self.o)
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self.i1 = mg.Signal.like(self.o)
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self.l0 = mg.Signal.like(self.o)
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self.l1 = mg.Signal.like(self.o)
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self.c = mg.Signal(2)
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self.comb += self.o.eq(self.sat_add((self.i0, self.i1),
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width=4, limits=(self.l0, self.l1), clipped=self.c))
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class SatAddTest(unittest.TestCase):
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def setUp(self):
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self.dut = DUT(width=4)
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# import migen.fhdl.verilog
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# print(mg.fhdl.verilog.convert(self.dut))
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def _sweep(self):
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def gen():
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for i0 in range(-8, 8):
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yield self.dut.i0.eq(i0)
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for i1 in range(-8, 8):
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yield self.dut.i1.eq(i1)
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yield
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def rec():
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l0 = yield self.dut.l0
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l1 = yield self.dut.l1
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for i in range(1 << 8):
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i0 = yield self.dut.i0
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i1 = yield self.dut.i1
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o = yield self.dut.o
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c = yield self.dut.c
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full = i0 + i1
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lim = full
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clip = 0
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if full < l0:
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lim = l0
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clip = 1
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if full > l1:
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lim = l1
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clip = 2
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with self.subTest(i0=i0, i1=i1):
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self.assertEqual(lim, o)
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self.assertEqual(clip, c)
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yield
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mg.run_simulation(self.dut, (gen(), rec()))
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def test_inst(self):
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pass
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def test_run(self):
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self._sweep()
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def test_limits(self):
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for l0 in -8, 0, 1, 7:
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for l1 in -8, 0, 1, 7:
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self.setUp()
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self.dut.l0.reset = l0
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self.dut.l1.reset = l1
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with self.subTest(l0=l0, l1=l1):
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self._sweep()
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import numpy as np
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from migen import *
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from migen.fhdl.verilog import convert
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from artiq.gateware.dsp import sawg
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from artiq.gateware.test.dsp.tools import xfer
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def _test_gen_dds(dut, o):
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yield from xfer(dut,
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a=dict(a0=10),
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p=dict(a0=0),
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f=dict(a0=1),
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)
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for i in range(256//dut.parallelism):
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yield
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o.append((yield from [(yield _) for _ in dut.xo]))
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def _test_channel():
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widths = sawg._Widths(t=8, a=4*8, p=8, f=16)
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orders = sawg._Orders(a=4, p=1, f=2)
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dut = sawg.SplineParallelDDS(widths, orders, parallelism=2)
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if False:
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print(convert(dut))
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else:
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o = []
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run_simulation(dut, _test_gen_dds(dut, o), vcd_name="dds.vcd")
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o = np.array(o)
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print(o[:, :])
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if __name__ == "__main__":
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_test_channel()
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import unittest
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import migen as mg
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from numpy import int32
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from artiq.coredevice import sawg, spline
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from artiq.language import (at_mu, now_mu, delay,
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core as core_language)
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from artiq.gateware.rtio.phy.sawg import Channel
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from artiq.sim import devices as sim_devices, time as sim_time
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class RTIOManager:
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def __init__(self):
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self.outputs = []
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def rtio_output(self, target, data):
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channel = target >> 8
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addr = target & 0xff
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self.outputs.append((now_mu(), channel, addr, data))
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def rtio_output_wide(self, *args, **kwargs):
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self.rtio_output(*args, **kwargs)
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def delay_mu(self, t):
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delay(t)
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def patch(self, mod):
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assert not hasattr(mod, "_saved")
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mod._saved = {}
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for name in "rtio_output rtio_output_wide delay_mu".split():
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mod._saved[name] = getattr(mod, name, None)
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setattr(mod, name, getattr(self, name))
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def unpatch(self, mod):
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mod.__dict__.update(mod._saved)
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del mod._saved
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class SAWGTest(unittest.TestCase):
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def setUp(self):
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core_language.set_time_manager(sim_time.Manager())
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self.rtio_manager = RTIOManager()
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self.rtio_manager.patch(spline)
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self.rtio_manager.patch(sawg)
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self.core = sim_devices.Core({})
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self.core.coarse_ref_period = 20/3
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self.core.ref_multiplier = 1
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self.t = self.core.coarse_ref_period
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self.channel = mg.ClockDomainsRenamer({"rio_phy": "sys"})(
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Channel(width=16, parallelism=2))
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self.driver = sawg.SAWG({"core": self.core}, channel_base=0,
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parallelism=self.channel.parallelism)
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def tearDown(self):
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self.rtio_manager.unpatch(spline)
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self.rtio_manager.unpatch(sawg)
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def test_instantiate(self):
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pass
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def test_make_events(self):
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d = self.driver
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d.offset.set(.9)
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delay(2*self.t)
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d.frequency0.set(.1)
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d.frequency1.set(.1)
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delay(2*self.t)
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d.offset.set(0)
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v = int(round((1 << 48) * .1 * self.t))
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self.assertEqual(
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self.rtio_manager.outputs, [
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(0., 1, 0, int(round(self.driver.offset.scale*.9))),
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(2.*self.t, 8, 0, int(round(
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(1 << self.driver.frequency0.width) *
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self.t/self.channel.parallelism*.1))),
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(2.*self.t, 3, 0, [int32(v), int32(v >> 32)]),
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(4.*self.t, 1, 0, 0),
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])
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def run_channel(self, events):
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def gen(dut, events):
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c = 0
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for time, channel, address, data in events:
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time //= self.t
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assert c <= time
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while c < time:
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yield
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c += 1
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for phy in dut.phys:
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yield phy.rtlink.o.stb.eq(0)
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rt = dut.phys[channel].rtlink.o
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if isinstance(data, list):
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data = sum(int(d) << (i*32) for i, d in enumerate(data))
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yield rt.data.eq(int(data))
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if hasattr(rt, "address"):
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yield rt.address.eq(address)
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yield rt.stb.eq(1)
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assert not (yield rt.busy)
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# print("{}: set ch {} to {}".format(time, channel, hex(data)))
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def log(dut, data, n):
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for i in range(n + dut.latency):
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yield
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data.append((yield from [(yield _) for _ in dut.o]))
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data = []
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# print(int(events[-1][0]) + 1)
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mg.run_simulation(self.channel, [
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gen(self.channel, events),
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log(self.channel, data, int(events[-1][0]//self.t) + 1)],
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vcd_name="dds.vcd")
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return data
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def test_run_channel(self):
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self.test_make_events()
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self.run_channel(self.rtio_manager.outputs)
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def test_coeff(self):
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import struct
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# these get discrete_compensate
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# [.1, .01, -.00001], [.1, .01, .00001, -.000000001]
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for v in [-.1], [.1, -.01]:
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ch = self.driver.offset
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p = ch.coeff_as_packed(v)
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t = ch.time_width
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w = ch.width
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p = [_ & 0xffffffff for _ in p]
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p0 = [int(round(vi*ch.scale*ch.time_scale**i))
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for i, vi in enumerate(v)]
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p0 = [struct.pack("<" + "_bhiiqqqq"[(w + i*t)//8], vi
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)[:(w + i*t)//8]
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for i, vi in enumerate(p0)]
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p0 = b"".join(p0)
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if len(p0) % 4:
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p0 += b"\x00"*(4 - len(p0) % 4)
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p0 = list(struct.unpack("<" + "I"*((len(p0) + 3)//4), p0))
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with self.subTest(v):
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self.assertEqual(p, p0)
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def test_linear(self):
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d = self.driver
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d.offset.set_coeff_mu([100, 10])
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delay(10*self.t)
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d.offset.set_coeff([0])
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delay(1*self.t)
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out = self.run_channel(self.rtio_manager.outputs)
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out = out[self.channel.latency + self.channel.u.latency:][:11]
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for i in range(len(out) - 1):
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with self.subTest(i):
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v = 100 + i*10
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self.assertEqual(out[i], [v, v])
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self.assertEqual(out[-1], [0, 0])
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def test_pack(self):
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ch = self.driver.offset
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self.assertEqual(ch.coeff_as_packed_mu([1]), [1])
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self.assertEqual(ch.coeff_as_packed_mu([1, 1 << 16]), [1, 1])
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self.assertEqual(ch.coeff_as_packed_mu([1, 1 << 32]), [1, 0])
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self.assertEqual(ch.coeff_as_packed_mu([0x1234, 0xa5a5a5a5]),
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[0xa5a51234, 0xa5a5])
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self.assertEqual(ch.coeff_as_packed_mu([1, 2, 3, 4]),
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[0x20001, 0x30000, 0, 4, 0])
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self.assertEqual(ch.coeff_as_packed_mu([-1, -2, -3, -4]),
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[0xfffeffff, 0xfffdffff, -1, -4, -1])
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self.assertEqual(ch.coeff_as_packed_mu([0, -1, 0, -1]),
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[0xffff0000, 0x0000ffff, 0, -1, -1])
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def test_smooth_linear(self):
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ch = self.driver.offset
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ch.smooth(.1, .2, 13*self.t, 1)
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ch.set(.2)
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delay(1*self.t)
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out = self.run_channel(self.rtio_manager.outputs)
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out = out[self.channel.latency + self.channel.u.latency:][:14]
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a = int(round(.1*ch.scale))
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||||
da = int(round(.1*ch.scale*(1 << ch.width)//13))
|
||||
for i in range(len(out) - 1):
|
||||
with self.subTest(i):
|
||||
v = a + (i*da >> ch.width)
|
||||
self.assertEqual(out[i], [v, v])
|
||||
a = int(round(.2*ch.scale))
|
||||
self.assertEqual(out[-1], [a, a])
|
||||
|
||||
def test_smooth_cubic(self):
|
||||
ch = self.driver.offset
|
||||
ch.smooth(.1, .2, 13*self.t, 3)
|
||||
ch.set(.2)
|
||||
delay(1*self.t)
|
||||
out = self.run_channel(self.rtio_manager.outputs)
|
||||
out = out[self.channel.latency + self.channel.u.latency:][:14]
|
||||
if False:
|
||||
import matplotlib.pyplot as plt
|
||||
plt.plot(sum(out, []))
|
||||
plt.show()
|
||||
|
||||
@unittest.skip("needs artiq.sim.time.TimeManager tweak for "
|
||||
"reverse timeline jumps")
|
||||
def test_demo_2tone(self):
|
||||
MHz = 1e-3
|
||||
ns = 1.
|
||||
self.sawg0 = self.driver
|
||||
|
||||
t_up = t_hold = t_down = 400*ns
|
||||
a1 = .3
|
||||
a2 = .4
|
||||
order = 3
|
||||
|
||||
self.sawg0.frequency0.set(10*MHz)
|
||||
self.sawg0.phase0.set(0.)
|
||||
self.sawg0.frequency1.set(1*MHz)
|
||||
self.sawg0.phase1.set(0.)
|
||||
self.sawg0.frequency2.set(13*MHz)
|
||||
self.sawg0.phase2.set(0.)
|
||||
t = now_mu()
|
||||
self.sawg0.amplitude1.smooth(.0, a1, t_up, order)
|
||||
at_mu(t)
|
||||
self.sawg0.amplitude2.smooth(.0, a2, t_up, order)
|
||||
self.sawg0.amplitude1.set(a1)
|
||||
self.sawg0.amplitude2.set(a2)
|
||||
delay(t_hold)
|
||||
t = now_mu()
|
||||
self.sawg0.amplitude1.smooth(a1, .0, t_down, order)
|
||||
at_mu(t)
|
||||
self.sawg0.amplitude2.smooth(a2, .0, t_down, order)
|
||||
self.sawg0.amplitude1.set(.0)
|
||||
self.sawg0.amplitude2.set(.0)
|
||||
|
||||
out = self.run_channel(self.rtio_manager.outputs)
|
||||
out = sum(out, [])
|
||||
if True:
|
||||
import matplotlib.pyplot as plt
|
||||
plt.plot(out)
|
||||
plt.show()
|
||||
|
||||
def test_fir_overflow(self):
|
||||
MHz = 1e-3
|
||||
ns = 1.
|
||||
f1 = self.driver.frequency1
|
||||
a1 = self.driver.amplitude1
|
||||
p1 = self.driver.phase1
|
||||
cfg = self.driver.config
|
||||
f1.set(1*MHz)
|
||||
a1.set(.99)
|
||||
delay(100*ns)
|
||||
p1.set(.5)
|
||||
delay(100*ns)
|
||||
a1.set(0)
|
||||
|
||||
out = self.run_channel(self.rtio_manager.outputs)
|
||||
out = sum(out, [])
|
||||
if False:
|
||||
import matplotlib.pyplot as plt
|
||||
plt.plot(out)
|
||||
plt.show()
|
||||
|
|
@ -1,70 +0,0 @@
|
|||
import numpy as np
|
||||
from operator import or_
|
||||
|
||||
from migen import *
|
||||
from migen.fhdl.verilog import convert
|
||||
|
||||
from artiq.gateware.rtio.phy.sawg import Channel
|
||||
from .tools import rtio_xfer
|
||||
|
||||
|
||||
def pack_tri(port, *v):
|
||||
r = 0
|
||||
w = 0
|
||||
for vi, p in zip(v, port.payload.flatten()):
|
||||
w += len(p)
|
||||
r |= int(vi*(1 << w))
|
||||
return r
|
||||
|
||||
|
||||
def gen_rtio(dut):
|
||||
yield
|
||||
yield from rtio_xfer(
|
||||
dut,
|
||||
a1=pack_tri(dut.a1.a, .1),
|
||||
f0=pack_tri(dut.b.f, .01234567),
|
||||
f1=pack_tri(dut.a1.f, .01234567),
|
||||
a2=pack_tri(dut.a1.a, .05),
|
||||
f2=pack_tri(dut.a1.f, .00534567),
|
||||
)
|
||||
|
||||
|
||||
def gen_log(dut, o, n):
|
||||
for i in range(3 + dut.latency):
|
||||
yield
|
||||
for i in range(n):
|
||||
yield
|
||||
o.append((yield from [(yield _) for _ in dut.o]))
|
||||
#o.append([(yield dut.a1.xo[0])])
|
||||
|
||||
|
||||
def _test_channel():
|
||||
width = 16
|
||||
|
||||
dut = ClockDomainsRenamer({"rio_phy": "sys"})(
|
||||
Channel(width=width, parallelism=4)
|
||||
)
|
||||
|
||||
if False:
|
||||
print(convert(dut))
|
||||
return
|
||||
|
||||
o = []
|
||||
run_simulation(
|
||||
dut,
|
||||
[gen_rtio(dut), gen_log(dut, o, 128)],
|
||||
vcd_name="dds.vcd")
|
||||
o = np.array(o)/(1 << (width - 1))
|
||||
o = o.ravel()
|
||||
np.savez_compressed("dds.npz", o=o)
|
||||
|
||||
import matplotlib.pyplot as plt
|
||||
fig, ax = plt.subplots(2)
|
||||
ax[0].step(np.arange(o.size), o)
|
||||
ax[1].psd(o, 1 << 10, Fs=1, noverlap=1 << 9, scale_by_freq=False)
|
||||
fig.savefig("dds.pdf")
|
||||
plt.show()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
_test_channel()
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
import numpy as np
|
||||
|
||||
from migen import *
|
||||
from migen.fhdl.verilog import convert
|
||||
|
||||
from artiq.gateware.dsp.spline import Spline
|
||||
from .tools import xfer
|
||||
|
||||
|
||||
def _test_gen_spline(dut, o):
|
||||
yield dut.o.ack.eq(1)
|
||||
yield from xfer(dut, i=dict(a0=0, a1=1, a2=2))
|
||||
for i in range(20):
|
||||
yield
|
||||
o.append((yield dut.o.a0))
|
||||
|
||||
|
||||
def _test_spline():
|
||||
dut = Spline(order=3, width=16, step=1)
|
||||
|
||||
if False:
|
||||
print(convert(dut))
|
||||
else:
|
||||
o = []
|
||||
run_simulation(dut, _test_gen_spline(dut, o), vcd_name="spline.vcd")
|
||||
o = np.array(o)
|
||||
print(o)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
_test_spline()
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
def set_dict(e, **k):
|
||||
for k, v in k.items():
|
||||
if isinstance(v, dict):
|
||||
yield from set_dict(getattr(e, k), **v)
|
||||
else:
|
||||
yield getattr(e, k).eq(v)
|
||||
|
||||
|
||||
def xfer(dut, **kw):
|
||||
ep = []
|
||||
for e, v in kw.items():
|
||||
e = getattr(dut, e)
|
||||
yield from set_dict(e, **v)
|
||||
ep.append(e)
|
||||
for e in ep:
|
||||
yield e.stb.eq(1)
|
||||
while ep:
|
||||
yield
|
||||
for e in ep[:]:
|
||||
if hasattr(e, "busy") and (yield e.busy):
|
||||
raise ValueError(e, "busy")
|
||||
if not hasattr(e, "ack") or (yield e.ack):
|
||||
yield e.stb.eq(0)
|
||||
ep.remove(e)
|
||||
|
||||
|
||||
def szip(*iters):
|
||||
active = {it: None for it in iters}
|
||||
while active:
|
||||
for it in list(active):
|
||||
while True:
|
||||
try:
|
||||
val = it.send(active[it])
|
||||
except StopIteration:
|
||||
del active[it]
|
||||
break
|
||||
if val is None:
|
||||
break
|
||||
else:
|
||||
active[it] = (yield val)
|
||||
val = (yield None)
|
||||
for it in active:
|
||||
active[it] = val
|
||||
|
||||
|
||||
def rtio_xfer(dut, **kwargs):
|
||||
yield from szip(*(
|
||||
xfer(dut.phys_named[k].rtlink, o={"data": v})
|
||||
for k, v in kwargs.items()))
|
||||
Loading…
Reference in New Issue