forked from M-Labs/artiq
wrpll.core: update for modified collector
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@ -76,32 +76,28 @@ class WRPLL(Module, AutoCSR):
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ddmtd_counter = Signal(N)
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self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
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self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_ref = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
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self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
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collector_update = Signal()
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self.sync.helper += collector_update.eq(ddmtd_counter == (2**N - 1))
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filter_cd = ClockDomainsRenamer("filter")
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self.submodules.collector = filter_cd(Collector(N))
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self.submodules.filter_helper = filter_cd(thls.make(filters.helper, data_width=48))
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self.submodules.filter_main = filter_cd(thls.make(filters.main, data_width=48))
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self.submodules.filter_helper = filter_cd(
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thls.make(filters.helper, data_width=48))
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self.submodules.filter_main = filter_cd(
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thls.make(filters.main, data_width=48))
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self.comb += [
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self.collector.tag_helper.eq(self.ddmtd_helper.h_tag),
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self.collector.tag_helper_update.eq(self.ddmtd_helper.h_tag_update),
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self.collector.tag_ref.eq(self.ddmtd_ref.h_tag),
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self.collector.ref_stb.eq(self.ddmtd_ref.h_tag_update),
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self.collector.tag_main.eq(self.ddmtd_main.h_tag),
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self.collector.tag_main_update.eq(self.ddmtd_main.h_tag_update)
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self.collector.main_stb.eq(self.ddmtd_main.h_tag_update)
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]
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# compensate the 1 cycle latency of the collector
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self.sync.helper += [
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self.filter_helper.input.eq(self.ddmtd_helper.h_tag),
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self.filter_helper.input_stb.eq(self.ddmtd_helper.h_tag_update)
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]
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self.comb += [
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self.filter_main.input.eq(self.collector.output),
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self.filter_main.input_stb.eq(collector_update)
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self.filter_helper.input.eq(self.collector.out_helper),
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self.filter_helper.input_stb.eq(self.collector.out_stb),
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self.filter_main.input.eq(self.collector.out_main),
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self.filter_main.input_stb.eq(self.collector.out_stb)
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]
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self.sync.helper += [
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