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runtime: add riscv

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This commit is contained in:
occheung 2021-08-06 11:05:17 +08:00
parent ecedec577c
commit e99061b013
2 changed files with 4 additions and 0 deletions
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1
artiq/firmware/runtime/Cargo.toml
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@ -28,6 +28,7 @@ logger_artiq = { path = "../liblogger_artiq" }
board_artiq = { path = "../libboard_artiq" } board_artiq = { path = "../libboard_artiq" }
proto_artiq = { path = "../libproto_artiq", features = ["log", "alloc"] } proto_artiq = { path = "../libproto_artiq", features = ["log", "alloc"] }
smoltcp = { version = "0.6.0", default-features = false, features = ["rust-1_28", "alloc", "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp"] } smoltcp = { version = "0.6.0", default-features = false, features = ["rust-1_28", "alloc", "ethernet", "proto-ipv4", "proto-ipv6", "socket-tcp"] }
riscv = { version = "0.6.0", features = ["inline-asm"] }
[dependencies.fringe] [dependencies.fringe]
git = "https://github.com/m-labs/libfringe" git = "https://github.com/m-labs/libfringe"

3
artiq/firmware/runtime/main.rs
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@ -25,6 +25,7 @@ extern crate board_misoc;
extern crate board_artiq; extern crate board_artiq;
extern crate logger_artiq; extern crate logger_artiq;
extern crate proto_artiq; extern crate proto_artiq;
extern crate riscv;
use core::cell::RefCell; use core::cell::RefCell;
use core::convert::TryFrom; use core::convert::TryFrom;
@ -41,6 +42,8 @@ use proto_artiq::{mgmt_proto, moninj_proto, rpc_proto, session_proto, kernel_pro
#[cfg(has_rtio_analyzer)] #[cfg(has_rtio_analyzer)]
use proto_artiq::analyzer_proto; use proto_artiq::analyzer_proto;
use riscv::register::{mcause, mepc};
mod rtio_clocking; mod rtio_clocking;
mod rtio_mgt; mod rtio_mgt;