forked from M-Labs/artiq
drtio: fix aux controller clock domain mistakes
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527757b471
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e9592105ce
@ -20,7 +20,8 @@ class Transmitter(Module, AutoCSR):
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self.aux_tx = CSR()
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self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))
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converter = stream.Converter(mem_dw, ll_dw)
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converter = ClockDomainsRenamer("rtio")(
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stream.Converter(mem_dw, ll_dw))
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self.submodules += converter
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# when continuously fed, the Converter outputs data continuously
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@ -107,7 +108,8 @@ class Receiver(Module, AutoCSR):
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mem_dw = max(min_mem_dw, ll_dw)
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self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))
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converter = stream.Converter(ll_dw, mem_dw)
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converter = ClockDomainsRenamer("rtio_rx")(
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stream.Converter(ll_dw, mem_dw))
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self.submodules += converter
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# when continuously drained, the Converter accepts data continuously
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