forked from M-Labs/artiq
sayma: add comments about CPLL line rate on KU GTH
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@ -169,6 +169,8 @@ class SatelliteBase(MiniSoC):
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# JESD204 DAC Channel Group
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# JESD204 DAC Channel Group
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class JDCG(Module, AutoCSR):
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class JDCG(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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# Kintex Ultrascale GTH, speed grade -1C:
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# CPLL linerate (D=1): 4.0 - 8.5 Gb/s
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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self.submodules.jesd = jesd204_tools.UltrascaleTX(
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platform, sys_crg, jesd_crg, dac)
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platform, sys_crg, jesd_crg, dac)
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