forked from M-Labs/artiq
doc/manual: list core device port
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@ -0,0 +1,22 @@
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Default network ports
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=====================
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+--------------------------+--------------+
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| Component | Default port |
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+==========================+==============+
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| Core device | 1381 |
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+--------------------------+--------------+
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| Master (notifications) | 3250 |
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+--------------------------+--------------+
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| Master (control) | 3251 |
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+--------------------------+--------------+
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| PDQ2 | 3252 |
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+--------------------------+--------------+
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| LDA | 3253 |
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+--------------------------+--------------+
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| Novatech 409B | 3254 |
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+--------------------------+--------------+
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| Thorlabs T-Cube | 3255 |
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+--------------------------+--------------+
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| NI PXI6733 | 3256 |
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+--------------------------+--------------+
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@ -17,4 +17,5 @@ Contents:
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ndsp_reference
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utilities
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fpga_board_ports
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default_network_ports
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faq
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@ -175,25 +175,3 @@ Usage example
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:ref: artiq.frontend.pxi6733_controller.get_argparser
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:prog: pxi6733_controller
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Default TCP port list
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---------------------
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When writing a new NDSP, choose a free TCP port and add it to this list.
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+--------------------------+--------------+
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| Component | Default port |
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+==========================+==============+
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| Master (notifications) | 3250 |
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+--------------------------+--------------+
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| Master (control) | 3251 |
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+--------------------------+--------------+
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| PDQ2 | 3252 |
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+--------------------------+--------------+
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| LDA | 3253 |
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+--------------------------+--------------+
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| Novatech 409B | 3254 |
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+--------------------------+--------------+
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| Thorlabs T-Cube | 3255 |
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+--------------------------+--------------+
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| NI PXI6733 | 3256 |
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+--------------------------+--------------+
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