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wrpll: add bit shift for collector helper output

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hartytp 2020-10-08 15:16:07 +08:00 committed by Sebastien Bourdeauducq
parent c9ae406ac6
commit e5e648bde1
1 changed files with 1 additions and 1 deletions
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2
artiq/gateware/drtio/wrpll/core.py
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@ -94,7 +94,7 @@ class WRPLL(Module, AutoCSR):
] ]
self.comb += [ self.comb += [
self.filter_helper.input.eq(self.collector.out_helper), self.filter_helper.input.eq(self.collector.out_helper << 22),
self.filter_helper.input_stb.eq(self.collector.out_stb), self.filter_helper.input_stb.eq(self.collector.out_stb),
self.filter_main.input.eq(self.collector.out_main), self.filter_main.input.eq(self.collector.out_main),
self.filter_main.input_stb.eq(self.collector.out_stb) self.filter_main.input_stb.eq(self.collector.out_stb)