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artiq_ddb_template: move satellite_cpu_target to core

This commit is contained in:
mwojcik 2023-10-18 13:02:54 +08:00 committed by Sébastien Bourdeauducq
parent b168f0bb4b
commit e480bbe8d8
2 changed files with 7 additions and 7 deletions
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6
artiq/coredevice/core.py
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@ -84,9 +84,11 @@ class Core:
"core", "ref_period", "coarse_ref_period", "ref_multiplier", "core", "ref_period", "coarse_ref_period", "ref_multiplier",
} }
def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="rv32g"): def __init__(self, dmgr, host, ref_period, ref_multiplier=8,
target="rv32g", satellite_cpu_targets={}):
self.ref_period = ref_period self.ref_period = ref_period
self.ref_multiplier = ref_multiplier self.ref_multiplier = ref_multiplier
self.satellite_cpu_targets = satellite_cpu_targets
self.target_cls = get_target_cls(target) self.target_cls = get_target_cls(target)
self.coarse_ref_period = ref_period*ref_multiplier self.coarse_ref_period = ref_period*ref_multiplier
if host is None: if host is None:
@ -159,7 +161,7 @@ class Core:
if subkernel_args[0][0] == 'self': if subkernel_args[0][0] == 'self':
self_arg = args[:1] self_arg = args[:1]
destination = subkernel_fn.artiq_embedded.destination destination = subkernel_fn.artiq_embedded.destination
destination_tgt = self.dmgr.ddb.get_satellite_cpu_target(destination) destination_tgt = self.satellite_cpu_targets[destination]
target = get_target_cls(destination_tgt)(subkernel_id=sid) target = get_target_cls(destination_tgt)(subkernel_id=sid)
object_map, kernel_library, _, _, _ = \ object_map, kernel_library, _, _, _ = \
self.compile(subkernel_fn, self_arg, {}, attribute_writeback=False, self.compile(subkernel_fn, self_arg, {}, attribute_writeback=False,

8
artiq/frontend/artiq_ddb_template.py
View File

@ -34,7 +34,7 @@ def process_header(output, description):
"type": "local", "type": "local",
"module": "artiq.coredevice.core", "module": "artiq.coredevice.core",
"class": "Core", "class": "Core",
"arguments": {{"host": core_addr, "ref_period": {ref_period}, "target": "{cpu_target}"}}, "arguments": {{"host": core_addr, "ref_period": {ref_period}, "target": "{cpu_target}", "satellite_cpu_targets": {{}} }},
}}, }},
"core_log": {{ "core_log": {{
"type": "controller", "type": "controller",
@ -60,8 +60,6 @@ def process_header(output, description):
"class": "CoreDMA" "class": "CoreDMA"
}}, }},
"satellite_cpu_targets": {{}},
"i2c_switch0": {{ "i2c_switch0": {{
"type": "local", "type": "local",
"module": "artiq.coredevice.i2c", "module": "artiq.coredevice.i2c",
@ -760,7 +758,7 @@ def process(output, primary_description, satellites):
print(textwrap.dedent(""" print(textwrap.dedent("""
# DEST#{dest} peripherals # DEST#{dest} peripherals
device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format( device_db["core"]["arguments"]["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
dest=destination, dest=destination,
target=get_cpu_target(description)), target=get_cpu_target(description)),
file=output) file=output)
@ -773,7 +771,7 @@ def process(output, primary_description, satellites):
print(textwrap.dedent(""" print(textwrap.dedent("""
# DEST#{dest} peripherals # DEST#{dest} peripherals
device_db["satellite_cpu_targets"][{dest}] = \"{target}\"""").format( device_db["core"]["arguments"]["satellite_cpu_targets"][{dest}] = \"{target}\"""").format(
dest=peripheral["drtio_destination"], dest=peripheral["drtio_destination"],
target=get_cpu_target(peripheral)), target=get_cpu_target(peripheral)),
file=output) file=output)