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coredevice/ad9912: port to NAC3

This commit is contained in:
Sebastien Bourdeauducq 2021-11-10 21:27:06 +08:00
parent 93f24c9f94
commit df87cc88d6
2 changed files with 148 additions and 139 deletions
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145
artiq/coredevice/ad9912.py
View File

@ -1,14 +1,16 @@
from numpy import int32, int64 from numpy import int32, int64
from artiq.language.types import TInt32, TInt64, TFloat, TTuple, TBool from artiq.language.core import KernelInvariant, nac3, kernel, portable
from artiq.language.core import kernel, delay, portable
from artiq.language.units import ms, us, ns from artiq.language.units import ms, us, ns
from artiq.coredevice.ad9912_reg import * from artiq.coredevice.ad9912_reg import *
from artiq.coredevice import spi2 as spi from artiq.coredevice.core import Core
from artiq.coredevice import urukul from artiq.coredevice.spi2 import *
from artiq.coredevice.urukul import *
from artiq.coredevice.ttl import TTLOut
@nac3
class AD9912: class AD9912:
""" """
AD9912 DDS channel on Urukul AD9912 DDS channel on Urukul
@ -27,10 +29,16 @@ class AD9912:
instance). instance).
""" """
core: KernelInvariant[Core]
cpld: KernelInvariant[CPLD]
bus: KernelInvariant[SPIMaster]
chip_select: KernelInvariant[int32]
pll_n: KernelInvariant[int32]
ftw_per_hz: KernelInvariant[float]
sw: KernelInvariant[TTLOut]
def __init__(self, dmgr, chip_select, cpld_device, sw_device=None, def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
pll_n=10): pll_n=10):
self.kernel_invariants = {"cpld", "core", "bus", "chip_select",
"pll_n", "ftw_per_hz"}
self.cpld = dmgr.get(cpld_device) self.cpld = dmgr.get(cpld_device)
self.core = self.cpld.core self.core = self.cpld.core
self.bus = self.cpld.bus self.bus = self.cpld.bus
@ -38,14 +46,13 @@ class AD9912:
self.chip_select = chip_select self.chip_select = chip_select
if sw_device: if sw_device:
self.sw = dmgr.get(sw_device) self.sw = dmgr.get(sw_device)
self.kernel_invariants.add("sw")
self.pll_n = pll_n self.pll_n = pll_n
sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
assert sysclk <= 1e9 assert sysclk <= 1e9
self.ftw_per_hz = 1 / sysclk * (int64(1) << 48) self.ftw_per_hz = 1 / sysclk * (1 << 48)
@kernel @kernel
def write(self, addr: TInt32, data: TInt32, length: TInt32): def write(self, addr: int32, data: int32, length: int32):
"""Variable length write to a register. """Variable length write to a register.
Up to 4 bytes. Up to 4 bytes.
@ -53,17 +60,17 @@ class AD9912:
:param data: Data to be written: int32 :param data: Data to be written: int32
:param length: Length in bytes (1-4) :param length: Length in bytes (1-4)
""" """
assert length > 0 # NAC3TODO assert length > 0
assert length <= 4 # NAC3TODO assert length <= 4
self.bus.set_config_mu(urukul.SPI_CONFIG, 16, self.bus.set_config_mu(SPI_CONFIG, 16,
urukul.SPIT_DDS_WR, self.chip_select) SPIT_DDS_WR, self.chip_select)
self.bus.write((addr | ((length - 1) << 13)) << 16) self.bus.write((addr | ((length - 1) << 13)) << 16)
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, length * 8, self.bus.set_config_mu(SPI_CONFIG | SPI_END, length * 8,
urukul.SPIT_DDS_WR, self.chip_select) SPIT_DDS_WR, self.chip_select)
self.bus.write(data << (32 - length * 8)) self.bus.write(data << (32 - length * 8))
@kernel @kernel
def read(self, addr: TInt32, length: TInt32) -> TInt32: def read(self, addr: int32, length: int32) -> int32:
"""Variable length read from a register. """Variable length read from a register.
Up to 4 bytes. Up to 4 bytes.
@ -71,18 +78,19 @@ class AD9912:
:param length: Length in bytes (1-4) :param length: Length in bytes (1-4)
:return: Data read :return: Data read
""" """
assert length > 0 # NAC3TODO assert length > 0
assert length <= 4 # NAC3TODO assert length <= 4
self.bus.set_config_mu(urukul.SPI_CONFIG, 16, self.bus.set_config_mu(SPI_CONFIG, 16,
urukul.SPIT_DDS_WR, self.chip_select) SPIT_DDS_WR, self.chip_select)
self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16) self.bus.write((addr | ((length - 1) << 13) | 0x8000) << 16)
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END self.bus.set_config_mu(SPI_CONFIG | SPI_END
| spi.SPI_INPUT, length * 8, | SPI_INPUT, length * 8,
urukul.SPIT_DDS_RD, self.chip_select) SPIT_DDS_RD, self.chip_select)
self.bus.write(0) self.bus.write(0)
data = self.bus.read() data = self.bus.read()
if length < 4: if length < 4:
data &= (1 << (length * 8)) - 1 # NAC3TODO data &= (1 << (length * 8)) - 1
data = data & (1 << (length * 8)) - 1
return data return data
@kernel @kernel
@ -94,25 +102,26 @@ class AD9912:
IO_UPDATE signal multiple times. IO_UPDATE signal multiple times.
""" """
# SPI mode # SPI mode
self.write(AD9912_SER_CONF, 0x99, length=1) self.write(AD9912_SER_CONF, 0x99, 1)
self.cpld.io_update.pulse(2 * us) self.cpld.io_update.pulse(2. * us)
# Verify chip ID and presence # Verify chip ID and presence
prodid = self.read(AD9912_PRODIDH, length=2) prodid = self.read(AD9912_PRODIDH, 2)
if (prodid != 0x1982) and (prodid != 0x1902): if (prodid != 0x1982) and (prodid != 0x1902):
raise ValueError("Urukul AD9912 product id mismatch") # NAC3TODO raise ValueError("Urukul AD9912 product id mismatch")
delay(50 * us) pass
self.core.delay(50. * us)
# HSTL power down, CMOS power down # HSTL power down, CMOS power down
self.write(AD9912_PWRCNTRL1, 0x80, length=1) self.write(AD9912_PWRCNTRL1, 0x80, 1)
self.cpld.io_update.pulse(2 * us) self.cpld.io_update.pulse(2. * us)
self.write(AD9912_N_DIV, self.pll_n // 2 - 2, length=1) self.write(AD9912_N_DIV, self.pll_n // 2 - 2, 1)
self.cpld.io_update.pulse(2 * us) self.cpld.io_update.pulse(2. * us)
# I_cp = 375 µA, VCO high range # I_cp = 375 µA, VCO high range
self.write(AD9912_PLLCFG, 0b00000101, length=1) self.write(AD9912_PLLCFG, 0b00000101, 1)
self.cpld.io_update.pulse(2 * us) self.cpld.io_update.pulse(2. * us)
delay(1 * ms) self.core.delay(1. * ms)
@kernel # NAC3TODO @kernel
def set_att_mu(self, att: TInt32): def set_att_mu(self, att: int32):
"""Set digital step attenuator in machine units. """Set digital step attenuator in machine units.
This method will write the attenuator settings of all four channels. This method will write the attenuator settings of all four channels.
@ -123,8 +132,8 @@ class AD9912:
""" """
self.cpld.set_att_mu(self.chip_select - 4, att) self.cpld.set_att_mu(self.chip_select - 4, att)
@kernel # NAC3TODO @kernel
def set_att(self, att: TFloat): def set_att(self, att: float):
"""Set digital step attenuator in SI units. """Set digital step attenuator in SI units.
This method will write the attenuator settings of all four channels. This method will write the attenuator settings of all four channels.
@ -136,7 +145,7 @@ class AD9912:
self.cpld.set_att(self.chip_select - 4, att) self.cpld.set_att(self.chip_select - 4, att)
@kernel @kernel
def get_att_mu(self) -> TInt32: def get_att_mu(self) -> int32:
"""Get digital step attenuator value in machine units. """Get digital step attenuator value in machine units.
.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att_mu` .. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att_mu`
@ -146,7 +155,7 @@ class AD9912:
return self.cpld.get_channel_att_mu(self.chip_select - 4) return self.cpld.get_channel_att_mu(self.chip_select - 4)
@kernel @kernel
def get_att(self) -> TFloat: def get_att(self) -> float:
"""Get digital step attenuator value in SI units. """Get digital step attenuator value in SI units.
.. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att` .. seealso:: :meth:`artiq.coredevice.urukul.CPLD.get_channel_att`
@ -156,7 +165,7 @@ class AD9912:
return self.cpld.get_channel_att(self.chip_select - 4) return self.cpld.get_channel_att(self.chip_select - 4)
@kernel @kernel
def set_mu(self, ftw: TInt64, pow_: TInt32): def set_mu(self, ftw: int64, pow_: int32):
"""Set profile 0 data in machine units. """Set profile 0 data in machine units.
After the SPI transfer, the shared IO update pin is pulsed to After the SPI transfer, the shared IO update pin is pulsed to
@ -166,19 +175,19 @@ class AD9912:
:param pow_: Phase tuning word: 16 bit unsigned. :param pow_: Phase tuning word: 16 bit unsigned.
""" """
# streaming transfer of FTW and POW # streaming transfer of FTW and POW
self.bus.set_config_mu(urukul.SPI_CONFIG, 16, self.bus.set_config_mu(SPI_CONFIG, 16,
urukul.SPIT_DDS_WR, self.chip_select) SPIT_DDS_WR, self.chip_select)
self.bus.write((AD9912_POW1 << 16) | (3 << 29)) self.bus.write((AD9912_POW1 << 16) | (3 << 29))
self.bus.set_config_mu(urukul.SPI_CONFIG, 32, self.bus.set_config_mu(SPI_CONFIG, 32,
urukul.SPIT_DDS_WR, self.chip_select) SPIT_DDS_WR, self.chip_select)
self.bus.write((pow_ << 16) | (int32(ftw >> 32) & 0xffff)) self.bus.write((pow_ << 16) | (int32(ftw >> int64(32)) & 0xffff))
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32, self.bus.set_config_mu(SPI_CONFIG | SPI_END, 32,
urukul.SPIT_DDS_WR, self.chip_select) SPIT_DDS_WR, self.chip_select)
self.bus.write(int32(ftw)) self.bus.write(int32(ftw))
self.cpld.io_update.pulse(10 * ns) self.cpld.io_update.pulse(10. * ns)
@kernel @kernel
def get_mu(self) -> TTuple([TInt64, TInt32]): def get_mu(self) -> tuple[int64, int32]:
"""Get the frequency tuning word and phase offset word. """Get the frequency tuning word and phase offset word.
.. seealso:: :meth:`get` .. seealso:: :meth:`get`
@ -191,34 +200,34 @@ class AD9912:
self.core.break_realtime() # Regain slack to perform second read self.core.break_realtime() # Regain slack to perform second read
low = self.read(AD9912_FTW3, 4) low = self.read(AD9912_FTW3, 4)
# Extract and return fields # Extract and return fields
ftw = (int64(high & 0xffff) << 32) | (int64(low) & int64(0xffffffff)) ftw = (int64(high & 0xffff) << int64(32)) | (int64(low) & int64(0xffffffff))
pow_ = (high >> 16) & 0x3fff pow_ = (high >> 16) & 0x3fff
return ftw, pow_ return ftw, pow_
@portable(flags={"fast-math"}) @portable
def frequency_to_ftw(self, frequency: TFloat) -> TInt64: def frequency_to_ftw(self, frequency: float) -> int64:
"""Returns the 48-bit frequency tuning word corresponding to the given """Returns the 48-bit frequency tuning word corresponding to the given
frequency. frequency.
""" """
return int64(round(self.ftw_per_hz * frequency)) & ( return int64(round(self.ftw_per_hz * frequency)) & (
(int64(1) << 48) - 1) (int64(1) << int64(48)) - int64(1))
@portable(flags={"fast-math"}) @portable
def ftw_to_frequency(self, ftw: TInt64) -> TFloat: def ftw_to_frequency(self, ftw: int64) -> float:
"""Returns the frequency corresponding to the given """Returns the frequency corresponding to the given
frequency tuning word. frequency tuning word.
""" """
return ftw / self.ftw_per_hz return float(ftw) / self.ftw_per_hz
@portable(flags={"fast-math"}) @portable
def turns_to_pow(self, phase: TFloat) -> TInt32: def turns_to_pow(self, phase: float) -> int32:
"""Returns the 16-bit phase offset word corresponding to the given """Returns the 16-bit phase offset word corresponding to the given
phase. phase.
""" """
return int32(round((1 << 14) * phase)) & 0xffff return int32(round(float(1 << 14) * phase)) & 0xffff
@portable(flags={"fast-math"}) @portable
def pow_to_turns(self, pow_: TInt32) -> TFloat: def pow_to_turns(self, pow_: int32) -> float:
"""Return the phase in turns corresponding to a given phase offset """Return the phase in turns corresponding to a given phase offset
word. word.
@ -228,7 +237,7 @@ class AD9912:
return pow_ / (1 << 14) return pow_ / (1 << 14)
@kernel @kernel
def set(self, frequency: TFloat, phase: TFloat = 0.0): def set(self, frequency: float, phase: float = 0.0):
"""Set profile 0 data in SI units. """Set profile 0 data in SI units.
.. seealso:: :meth:`set_mu` .. seealso:: :meth:`set_mu`
@ -240,7 +249,7 @@ class AD9912:
self.turns_to_pow(phase)) self.turns_to_pow(phase))
@kernel @kernel
def get(self) -> TTuple([TFloat, TFloat]): def get(self) -> tuple[float, float]:
"""Get the frequency and phase. """Get the frequency and phase.
.. seealso:: :meth:`get_mu` .. seealso:: :meth:`get_mu`
@ -253,8 +262,8 @@ class AD9912:
# Convert and return # Convert and return
return self.ftw_to_frequency(ftw), self.pow_to_turns(pow_) return self.ftw_to_frequency(ftw), self.pow_to_turns(pow_)
@kernel # NAC3TODO @kernel
def cfg_sw(self, state: TBool): def cfg_sw(self, state: bool):
"""Set CPLD CFG RF switch state. The RF switch is controlled by the """Set CPLD CFG RF switch state. The RF switch is controlled by the
logical or of the CPLD configuration shift register logical or of the CPLD configuration shift register
RF switch bit and the SW TTL line (if used). RF switch bit and the SW TTL line (if used).

142
artiq/coredevice/ad9912_reg.py
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@ -1,78 +1,78 @@
# auto-generated, do not edit # auto-generated, do not edit
from numpy import int32
from artiq.language.core import portable from artiq.language.core import portable
from artiq.language.types import TInt32
AD9912_SER_CONF = 0x000 AD9912_SER_CONF = 0x000
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_SDOACTIVE_SET(x: TInt32) -> TInt32: def AD9912_SDOACTIVE_SET(x: int32) -> int32:
return (x & 0x1) << 0 return (x & 0x1) << 0
@portable @portable
def AD9912_SDOACTIVE_GET(x: TInt32) -> TInt32: def AD9912_SDOACTIVE_GET(x: int32) -> int32:
return (x >> 0) & 0x1 return (x >> 0) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_LSBFIRST_SET(x: TInt32) -> TInt32: def AD9912_LSBFIRST_SET(x: int32) -> int32:
return (x & 0x1) << 1 return (x & 0x1) << 1
@portable @portable
def AD9912_LSBFIRST_GET(x: TInt32) -> TInt32: def AD9912_LSBFIRST_GET(x: int32) -> int32:
return (x >> 1) & 0x1 return (x >> 1) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_SOFTRESET_SET(x: TInt32) -> TInt32: def AD9912_SOFTRESET_SET(x: int32) -> int32:
return (x & 0x1) << 2 return (x & 0x1) << 2
@portable @portable
def AD9912_SOFTRESET_GET(x: TInt32) -> TInt32: def AD9912_SOFTRESET_GET(x: int32) -> int32:
return (x >> 2) & 0x1 return (x >> 2) & 0x1
# default: 0x01, access: R/W # default: 0x01, access: R/W
@portable @portable
def AD9912_LONGINSN_SET(x: TInt32) -> TInt32: def AD9912_LONGINSN_SET(x: int32) -> int32:
return (x & 0x1) << 3 return (x & 0x1) << 3
@portable @portable
def AD9912_LONGINSN_GET(x: TInt32) -> TInt32: def AD9912_LONGINSN_GET(x: int32) -> int32:
return (x >> 3) & 0x1 return (x >> 3) & 0x1
# default: 0x01, access: R/W # default: 0x01, access: R/W
@portable @portable
def AD9912_LONGINSN_M_SET(x: TInt32) -> TInt32: def AD9912_LONGINSN_M_SET(x: int32) -> int32:
return (x & 0x1) << 4 return (x & 0x1) << 4
@portable @portable
def AD9912_LONGINSN_M_GET(x: TInt32) -> TInt32: def AD9912_LONGINSN_M_GET(x: int32) -> int32:
return (x >> 4) & 0x1 return (x >> 4) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_SOFTRESET_M_SET(x: TInt32) -> TInt32: def AD9912_SOFTRESET_M_SET(x: int32) -> int32:
return (x & 0x1) << 5 return (x & 0x1) << 5
@portable @portable
def AD9912_SOFTRESET_M_GET(x: TInt32) -> TInt32: def AD9912_SOFTRESET_M_GET(x: int32) -> int32:
return (x >> 5) & 0x1 return (x >> 5) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_LSBFIRST_M_SET(x: TInt32) -> TInt32: def AD9912_LSBFIRST_M_SET(x: int32) -> int32:
return (x & 0x1) << 6 return (x & 0x1) << 6
@portable @portable
def AD9912_LSBFIRST_M_GET(x: TInt32) -> TInt32: def AD9912_LSBFIRST_M_GET(x: int32) -> int32:
return (x >> 6) & 0x1 return (x >> 6) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_SDOACTIVE_M_SET(x: TInt32) -> TInt32: def AD9912_SDOACTIVE_M_SET(x: int32) -> int32:
return (x & 0x1) << 7 return (x & 0x1) << 7
@portable @portable
def AD9912_SDOACTIVE_M_GET(x: TInt32) -> TInt32: def AD9912_SDOACTIVE_M_GET(x: int32) -> int32:
return (x >> 7) & 0x1 return (x >> 7) & 0x1
@ -83,118 +83,118 @@ AD9912_PRODIDH = 0x003
AD9912_SER_OPT1 = 0x004 AD9912_SER_OPT1 = 0x004
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_READ_BUF_SET(x: TInt32) -> TInt32: def AD9912_READ_BUF_SET(x: int32) -> int32:
return (x & 0x1) << 0 return (x & 0x1) << 0
@portable @portable
def AD9912_READ_BUF_GET(x: TInt32) -> TInt32: def AD9912_READ_BUF_GET(x: int32) -> int32:
return (x >> 0) & 0x1 return (x >> 0) & 0x1
AD9912_SER_OPT2 = 0x005 AD9912_SER_OPT2 = 0x005
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_RED_UPDATE_SET(x: TInt32) -> TInt32: def AD9912_RED_UPDATE_SET(x: int32) -> int32:
return (x & 0x1) << 0 return (x & 0x1) << 0
@portable @portable
def AD9912_RED_UPDATE_GET(x: TInt32) -> TInt32: def AD9912_RED_UPDATE_GET(x: int32) -> int32:
return (x >> 0) & 0x1 return (x >> 0) & 0x1
AD9912_PWRCNTRL1 = 0x010 AD9912_PWRCNTRL1 = 0x010
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_PD_DIGITAL_SET(x: TInt32) -> TInt32: def AD9912_PD_DIGITAL_SET(x: int32) -> int32:
return (x & 0x1) << 0 return (x & 0x1) << 0
@portable @portable
def AD9912_PD_DIGITAL_GET(x: TInt32) -> TInt32: def AD9912_PD_DIGITAL_GET(x: int32) -> int32:
return (x >> 0) & 0x1 return (x >> 0) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_PD_FULL_SET(x: TInt32) -> TInt32: def AD9912_PD_FULL_SET(x: int32) -> int32:
return (x & 0x1) << 1 return (x & 0x1) << 1
@portable @portable
def AD9912_PD_FULL_GET(x: TInt32) -> TInt32: def AD9912_PD_FULL_GET(x: int32) -> int32:
return (x >> 1) & 0x1 return (x >> 1) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_PD_SYSCLK_SET(x: TInt32) -> TInt32: def AD9912_PD_SYSCLK_SET(x: int32) -> int32:
return (x & 0x1) << 4 return (x & 0x1) << 4
@portable @portable
def AD9912_PD_SYSCLK_GET(x: TInt32) -> TInt32: def AD9912_PD_SYSCLK_GET(x: int32) -> int32:
return (x >> 4) & 0x1 return (x >> 4) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_EN_DOUBLER_SET(x: TInt32) -> TInt32: def AD9912_EN_DOUBLER_SET(x: int32) -> int32:
return (x & 0x1) << 5 return (x & 0x1) << 5
@portable @portable
def AD9912_EN_DOUBLER_GET(x: TInt32) -> TInt32: def AD9912_EN_DOUBLER_GET(x: int32) -> int32:
return (x >> 5) & 0x1 return (x >> 5) & 0x1
# default: 0x01, access: R/W # default: 0x01, access: R/W
@portable @portable
def AD9912_EN_CMOS_SET(x: TInt32) -> TInt32: def AD9912_EN_CMOS_SET(x: int32) -> int32:
return (x & 0x1) << 6 return (x & 0x1) << 6
@portable @portable
def AD9912_EN_CMOS_GET(x: TInt32) -> TInt32: def AD9912_EN_CMOS_GET(x: int32) -> int32:
return (x >> 6) & 0x1 return (x >> 6) & 0x1
# default: 0x01, access: R/W # default: 0x01, access: R/W
@portable @portable
def AD9912_PD_HSTL_SET(x: TInt32) -> TInt32: def AD9912_PD_HSTL_SET(x: int32) -> int32:
return (x & 0x1) << 7 return (x & 0x1) << 7
@portable @portable
def AD9912_PD_HSTL_GET(x: TInt32) -> TInt32: def AD9912_PD_HSTL_GET(x: int32) -> int32:
return (x >> 7) & 0x1 return (x >> 7) & 0x1
AD9912_PWRCNTRL2 = 0x012 AD9912_PWRCNTRL2 = 0x012
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_DDS_RESET_SET(x: TInt32) -> TInt32: def AD9912_DDS_RESET_SET(x: int32) -> int32:
return (x & 0x1) << 0 return (x & 0x1) << 0
@portable @portable
def AD9912_DDS_RESET_GET(x: TInt32) -> TInt32: def AD9912_DDS_RESET_GET(x: int32) -> int32:
return (x >> 0) & 0x1 return (x >> 0) & 0x1
AD9912_PWRCNTRL3 = 0x013 AD9912_PWRCNTRL3 = 0x013
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_S_DIV_RESET_SET(x: TInt32) -> TInt32: def AD9912_S_DIV_RESET_SET(x: int32) -> int32:
return (x & 0x1) << 1 return (x & 0x1) << 1
@portable @portable
def AD9912_S_DIV_RESET_GET(x: TInt32) -> TInt32: def AD9912_S_DIV_RESET_GET(x: int32) -> int32:
return (x >> 1) & 0x1 return (x >> 1) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_S_DIV2_RESET_SET(x: TInt32) -> TInt32: def AD9912_S_DIV2_RESET_SET(x: int32) -> int32:
return (x & 0x1) << 3 return (x & 0x1) << 3
@portable @portable
def AD9912_S_DIV2_RESET_GET(x: TInt32) -> TInt32: def AD9912_S_DIV2_RESET_GET(x: int32) -> int32:
return (x >> 3) & 0x1 return (x >> 3) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_PD_FUND_SET(x: TInt32) -> TInt32: def AD9912_PD_FUND_SET(x: int32) -> int32:
return (x & 0x1) << 7 return (x & 0x1) << 7
@portable @portable
def AD9912_PD_FUND_GET(x: TInt32) -> TInt32: def AD9912_PD_FUND_GET(x: int32) -> int32:
return (x >> 7) & 0x1 return (x >> 7) & 0x1
@ -203,38 +203,38 @@ AD9912_N_DIV = 0x020
AD9912_PLLCFG = 0x022 AD9912_PLLCFG = 0x022
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_PLL_ICP_SET(x: TInt32) -> TInt32: def AD9912_PLL_ICP_SET(x: int32) -> int32:
return (x & 0x3) << 0 return (x & 0x3) << 0
@portable @portable
def AD9912_PLL_ICP_GET(x: TInt32) -> TInt32: def AD9912_PLL_ICP_GET(x: int32) -> int32:
return (x >> 0) & 0x3 return (x >> 0) & 0x3
# default: 0x01, access: R/W # default: 0x01, access: R/W
@portable @portable
def AD9912_VCO_RANGE_SET(x: TInt32) -> TInt32: def AD9912_VCO_RANGE_SET(x: int32) -> int32:
return (x & 0x1) << 2 return (x & 0x1) << 2
@portable @portable
def AD9912_VCO_RANGE_GET(x: TInt32) -> TInt32: def AD9912_VCO_RANGE_GET(x: int32) -> int32:
return (x >> 2) & 0x1 return (x >> 2) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_PLL_REF2X_SET(x: TInt32) -> TInt32: def AD9912_PLL_REF2X_SET(x: int32) -> int32:
return (x & 0x1) << 3 return (x & 0x1) << 3
@portable @portable
def AD9912_PLL_REF2X_GET(x: TInt32) -> TInt32: def AD9912_PLL_REF2X_GET(x: int32) -> int32:
return (x >> 3) & 0x1 return (x >> 3) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_VCO_AUTO_RANGE_SET(x: TInt32) -> TInt32: def AD9912_VCO_AUTO_RANGE_SET(x: int32) -> int32:
return (x & 0x1) << 7 return (x & 0x1) << 7
@portable @portable
def AD9912_VCO_AUTO_RANGE_GET(x: TInt32) -> TInt32: def AD9912_VCO_AUTO_RANGE_GET(x: int32) -> int32:
return (x >> 7) & 0x1 return (x >> 7) & 0x1
@ -245,20 +245,20 @@ AD9912_S_DIVH = 0x105
AD9912_S_DIV_CFG = 0x106 AD9912_S_DIV_CFG = 0x106
# default: 0x01, access: R/W # default: 0x01, access: R/W
@portable @portable
def AD9912_S_DIV2_SET(x: TInt32) -> TInt32: def AD9912_S_DIV2_SET(x: int32) -> int32:
return (x & 0x1) << 0 return (x & 0x1) << 0
@portable @portable
def AD9912_S_DIV2_GET(x: TInt32) -> TInt32: def AD9912_S_DIV2_GET(x: int32) -> int32:
return (x >> 0) & 0x1 return (x >> 0) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_S_DIV_FALL_SET(x: TInt32) -> TInt32: def AD9912_S_DIV_FALL_SET(x: int32) -> int32:
return (x & 0x1) << 7 return (x & 0x1) << 7
@portable @portable
def AD9912_S_DIV_FALL_GET(x: TInt32) -> TInt32: def AD9912_S_DIV_FALL_GET(x: int32) -> int32:
return (x >> 7) & 0x1 return (x >> 7) & 0x1
@ -281,31 +281,31 @@ AD9912_POW1 = 0x1ad
AD9912_HSTL = 0x200 AD9912_HSTL = 0x200
# default: 0x01, access: R/W # default: 0x01, access: R/W
@portable @portable
def AD9912_HSTL_CFG_SET(x: TInt32) -> TInt32: def AD9912_HSTL_CFG_SET(x: int32) -> int32:
return (x & 0x3) << 0 return (x & 0x3) << 0
@portable @portable
def AD9912_HSTL_CFG_GET(x: TInt32) -> TInt32: def AD9912_HSTL_CFG_GET(x: int32) -> int32:
return (x >> 0) & 0x3 return (x >> 0) & 0x3
# default: 0x01, access: R/W # default: 0x01, access: R/W
@portable @portable
def AD9912_HSTL_OPOL_SET(x: TInt32) -> TInt32: def AD9912_HSTL_OPOL_SET(x: int32) -> int32:
return (x & 0x1) << 4 return (x & 0x1) << 4
@portable @portable
def AD9912_HSTL_OPOL_GET(x: TInt32) -> TInt32: def AD9912_HSTL_OPOL_GET(x: int32) -> int32:
return (x >> 4) & 0x1 return (x >> 4) & 0x1
AD9912_CMOS = 0x201 AD9912_CMOS = 0x201
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_CMOS_MUX_SET(x: TInt32) -> TInt32: def AD9912_CMOS_MUX_SET(x: int32) -> int32:
return (x & 0x1) << 0 return (x & 0x1) << 0
@portable @portable
def AD9912_CMOS_MUX_GET(x: TInt32) -> TInt32: def AD9912_CMOS_MUX_GET(x: int32) -> int32:
return (x >> 0) & 0x1 return (x >> 0) & 0x1
@ -316,29 +316,29 @@ AD9912_FSC1 = 0x40c
AD9912_HSR_A_CFG = 0x500 AD9912_HSR_A_CFG = 0x500
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_HSR_A_HARMONIC_SET(x: TInt32) -> TInt32: def AD9912_HSR_A_HARMONIC_SET(x: int32) -> int32:
return (x & 0xf) << 0 return (x & 0xf) << 0
@portable @portable
def AD9912_HSR_A_HARMONIC_GET(x: TInt32) -> TInt32: def AD9912_HSR_A_HARMONIC_GET(x: int32) -> int32:
return (x >> 0) & 0xf return (x >> 0) & 0xf
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_HSR_A_MAG2X_SET(x: TInt32) -> TInt32: def AD9912_HSR_A_MAG2X_SET(x: int32) -> int32:
return (x & 0x1) << 6 return (x & 0x1) << 6
@portable @portable
def AD9912_HSR_A_MAG2X_GET(x: TInt32) -> TInt32: def AD9912_HSR_A_MAG2X_GET(x: int32) -> int32:
return (x >> 6) & 0x1 return (x >> 6) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_HSR_A_EN_SET(x: TInt32) -> TInt32: def AD9912_HSR_A_EN_SET(x: int32) -> int32:
return (x & 0x1) << 7 return (x & 0x1) << 7
@portable @portable
def AD9912_HSR_A_EN_GET(x: TInt32) -> TInt32: def AD9912_HSR_A_EN_GET(x: int32) -> int32:
return (x >> 7) & 0x1 return (x >> 7) & 0x1
@ -351,29 +351,29 @@ AD9912_HSR_A_POW1 = 0x504
AD9912_HSR_B_CFG = 0x505 AD9912_HSR_B_CFG = 0x505
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_HSR_B_HARMONIC_SET(x: TInt32) -> TInt32: def AD9912_HSR_B_HARMONIC_SET(x: int32) -> int32:
return (x & 0xf) << 0 return (x & 0xf) << 0
@portable @portable
def AD9912_HSR_B_HARMONIC_GET(x: TInt32) -> TInt32: def AD9912_HSR_B_HARMONIC_GET(x: int32) -> int32:
return (x >> 0) & 0xf return (x >> 0) & 0xf
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_HSR_B_MAG2X_SET(x: TInt32) -> TInt32: def AD9912_HSR_B_MAG2X_SET(x: int32) -> int32:
return (x & 0x1) << 6 return (x & 0x1) << 6
@portable @portable
def AD9912_HSR_B_MAG2X_GET(x: TInt32) -> TInt32: def AD9912_HSR_B_MAG2X_GET(x: int32) -> int32:
return (x >> 6) & 0x1 return (x >> 6) & 0x1
# default: 0x00, access: R/W # default: 0x00, access: R/W
@portable @portable
def AD9912_HSR_B_EN_SET(x: TInt32) -> TInt32: def AD9912_HSR_B_EN_SET(x: int32) -> int32:
return (x & 0x1) << 7 return (x & 0x1) << 7
@portable @portable
def AD9912_HSR_B_EN_GET(x: TInt32) -> TInt32: def AD9912_HSR_B_EN_GET(x: int32) -> int32:
return (x >> 7) & 0x1 return (x >> 7) & 0x1