Revert "Globally update UART baudrate to 921600."

This reverts commit b29e2d5bfe.

This broke flterm firmware upload, which was the entire point
of the whole exercise.

artiq/frontend/artiq_devtool.py

@@ -100,7 +100,7 @@ def main():
 
             logger.info("Booting runtime")
             flterm = run_command(
-                "{env} python3 flterm.py {serial} --speed 921600" +
+                "{env} python3 flterm.py {serial} " +
                 "--kernel /tmp/{tmp}/runtime.bin " +
                 ("--upload-only" if action == "boot" else "--output-only"))
             artiq_flash = run_command(
@@ -151,7 +151,7 @@ def main():
 
             logger.info("Connecting to device")
             flterm = run_command(
-                "{env} python3 flterm.py {serial} --speed 921600 --output-only")
+                "{env} python3 flterm.py {serial} --output-only")
             drain(flterm)
 
         else:

artiq/gateware/targets/kc705_dds.py

@@ -112,7 +112,6 @@ class _NIST_Ions(MiniSoC, AMPSoC):
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,
-                         uart_baudrate=921600,
                          **kwargs)
         AMPSoC.__init__(self)
         if isinstance(self.platform.toolchain, XilinxVivadoToolchain):

artiq/gateware/targets/kc705_drtio_master.py

@@ -33,7 +33,6 @@ class Master(MiniSoC, AMPSoC):
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,
-                         uart_baudrate=921600,
                          **kwargs)
         AMPSoC.__init__(self)
 

artiq/gateware/targets/kc705_drtio_satellite.py

@@ -131,7 +131,6 @@ class Satellite(BaseSoC):
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
                  ident=artiq_version,
-                 uart_baudrate=921600,
                  **kwargs)
 
         platform = self.platform

artiq/gateware/targets/phaser.py

@@ -169,7 +169,6 @@ class Phaser(MiniSoC, AMPSoC):
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,
-                         uart_baudrate=921600,
                          **kwargs)
         AMPSoC.__init__(self)
         self.platform.toolchain.bitstream_commands.extend([

artiq/gateware/targets/pipistrello.py

@@ -160,7 +160,6 @@ class Demo(BaseSoC, AMPSoC):
                          l2_size=64*1024,
                          ident=artiq_version,
                          clk_freq=75*1000*1000,
-                         uart_baudrate=921600,
                          **kwargs)
         AMPSoC.__init__(self)
 

doc/manual/installing_from_source.rst

@@ -187,7 +187,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
 
 * Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
 
-        $ flterm /dev/ttyUSB1 --speed 921600
+        $ flterm /dev/ttyUSB1
         MiSoC BIOS   http://m-labs.hk
         [...]
         Booting from flash...
@@ -197,7 +197,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
 
 .. note:: flterm is part of MiSoC. If you installed MiSoC with ``setup.py develop --user``, the flterm launcher is in ``~/.local/bin``.
 
-The communication parameters are 921600 8-N-1. Ensure that your user has access
+The communication parameters are 115200 8-N-1. Ensure that your user has access
 to the serial device (``sudo adduser $USER dialout`` assuming standard setup).
 
 .. _installing-the-host-side-software: