forked from M-Labs/artiq
rtio: use FWFT FIFO with no buffering. This fixes replace operations.
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@ -1,6 +1,6 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered
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from migen.genlib.fifo import SyncFIFO
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from artiqlib.rtio.rbus import get_fine_ts_width
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@ -31,7 +31,7 @@ class _RTIOBankO(Module):
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fifos = []
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for n, chif in enumerate(rbus):
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fifo = SyncFIFOBuffered([
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fifo = SyncFIFO([
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("timestamp", counter_width+fine_ts_width), ("value", 2)],
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2 if chif.mini else fifo_depth)
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self.submodules += fifo
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@ -89,7 +89,7 @@ class _RTIOBankI(Module):
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self.sync += If(~chif.oe & chif.o_stb,
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sensitivity.eq(chif.o_value))
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fifo = SyncFIFOBuffered([
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fifo = SyncFIFO([
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("timestamp", counter_width+fine_ts_width), ("value", 1)],
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fifo_depth)
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self.submodules += fifo
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