kasli_sawgmaster: initialize SAWG phase according to RTIO TSC

2019-01-27 09:49:31 +08:00 · 2019-01-27 09:49:31 +08:00 · d1ef036948
commit d1ef036948
parent 9966e789fc
1 changed files with 1 additions and 0 deletions
--- a/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py
+++ b/artiq/examples/kasli_sawgmaster/repository/sines_urukul_sayma.py
@ -51,6 +51,7 @@ class SinesUrukulSayma(EnvExperiment):
                delay(1*ms)
                sawg.amplitude1.set(.4)
                sawg.frequency0.set_mu(sawg_ftw)
+                sawg.phase0.set_mu(sawg_ftw*now_mu() >> 17)

            while self.drtio_is_up():
                pass