forked from M-Labs/artiq
phaser: fix README
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@ -28,7 +28,7 @@ The additions and modifications to ARTIQ that were implemented for this project
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* The CORDIC core has been reused from the PDQ2 gateware
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https://github.com/m-labs/pdq2
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* The Migen/MiSoC JESD204B core: https://github.com/enjoy-digital/litejesd204b
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:
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Installation
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------------
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@ -38,7 +38,8 @@ Please refer to the manual for more details:
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https://m-labs.hk/artiq/manual-release-2/index.html
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* Set up a new conda environment and activate it.
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* Checkout the ARTIQ phaser branch::
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* Checkout the ARTIQ phaser branch: ::
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git clone -b phaser https://github.com/m-labs/artiq.git
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* Install the standard ARTIQ runtime/install dependencies.
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@ -70,9 +71,11 @@ Setup
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- on JP3 (will force output enable on FXLA108)
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* Compile the ARTIQ Phaser bitstream, bios, and runtime (c.f. ARTIQ manual): ::
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python -m artiq.gateware.targets.kc705 -H phaser --toolchain vivado
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* Run the following OpenOCD commands to flash the ARTIQ transmitter design: ::
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init
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jtagspi_init 0 bscan_spi_xc7k325t.bit
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jtagspi_program misoc_phaser_kc705/gateware/top.bin 0x000000
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