forked from M-Labs/artiq
test_cache: port to NAC3
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import unittest
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from numpy import int32
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from artiq.experiment import *
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from artiq.experiment import *
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from artiq.coredevice.core import Core
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from artiq.coredevice.cache import CoreCache
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from artiq.coredevice.exceptions import CacheError
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from artiq.coredevice.exceptions import CacheError
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from artiq.test.hardware_testbench import ExperimentCase
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from artiq.test.hardware_testbench import ExperimentCase
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@nac3
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class _Cache(EnvExperiment):
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class _Cache(EnvExperiment):
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core: KernelInvariant[Core]
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core_cache: KernelInvariant[CoreCache]
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def build(self):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("core")
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self.setattr_device("core_cache")
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self.setattr_device("core_cache")
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@kernel
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@kernel
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def get(self, key):
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def get(self, key: str) -> list[int32]:
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return self.core_cache.get(key)
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return self.core_cache.get(key)
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@kernel
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@kernel
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def put(self, key, value):
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def put(self, key: str, value: list[int32]):
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self.core_cache.put(key, value)
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self.core_cache.put(key, value)
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@kernel
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@kernel
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def get_put(self, key, value):
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def get_put(self, key: str, value: list[int32]):
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self.get(key)
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self.get(key)
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self.put(key, value)
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self.put(key, value)
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@unittest.skip("NAC3TODO https://git.m-labs.hk/M-Labs/nac3/issues/299")
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class CacheTest(ExperimentCase):
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class CacheTest(ExperimentCase):
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def test_get_empty(self):
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def test_get_empty(self):
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exp = self.create(_Cache)
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exp = self.create(_Cache)
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