forked from M-Labs/artiq
ttl_serdes_generic: fix/upgrade test
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a5825184b7
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@ -115,166 +115,3 @@ class InOut(Module):
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self.submodules += pe
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self.comb += pe.i.eq(serdes.i ^ Replicate(i_d, serdes_width))
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self.sync.rio_phy += self.rtlink.i.fine_ts.eq(pe.o)
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class _FakeSerdes(Module):
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def __init__(self):
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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class _OutputTB(Module):
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def __init__(self):
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serdes = _FakeSerdes()
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self.submodules.dut = RenameClockDomains(Output(serdes),
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{"rio_phy": "sys"})
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def gen_simulation(self, selfp):
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.fine_ts = 1
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selfp.dut.rtlink.o.stb = 1
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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selfp.dut.rtlink.o.data = 0
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selfp.dut.rtlink.o.fine_ts = 2
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selfp.dut.rtlink.o.stb = 1
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yield
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yield
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.fine_ts = 7
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selfp.dut.rtlink.o.stb = 1
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for _ in range(6):
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# note that stb stays active; output should not change
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yield
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class _InOutTB(Module):
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def __init__(self):
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self.serdes = _FakeSerdes()
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self.submodules.dut = RenameClockDomains(InOut(self.serdes),
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{"rio_phy": "sys",
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"rio": "sys"})
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def check_input(self, selfp, stb, fine_ts=None):
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if stb != selfp.dut.rtlink.i.stb:
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print("KO rtlink.i.stb should be {} but is {}"
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.format(stb, selfp.dut.rtlink.i.stb))
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elif fine_ts is not None and fine_ts != selfp.dut.rtlink.i.fine_ts:
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print("KO rtlink.i.fine_ts should be {} but is {}"
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.format(fine_ts, selfp.dut.rtlink.i.fine_ts))
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else:
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print("OK")
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def check_output(self, selfp, data):
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if selfp.serdes.o != data:
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print("KO io.o should be {} but is {}".format(data, selfp.serdes.o))
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else:
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print("OK")
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def check_output_enable(self, selfp, oe):
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if selfp.serdes.oe != oe:
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print("KO io.oe should be {} but is {}".format(oe, selfp.serdes.oe))
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else:
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print("OK")
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def gen_simulation(self, selfp):
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selfp.dut.rtlink.o.address = 2
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selfp.dut.rtlink.o.data = 0b11
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selfp.dut.rtlink.o.stb = 1 # set sensitivity to rising + falling
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yield
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selfp.dut.rtlink.o.stb = 0
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self.check_output_enable(selfp, 0)
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yield
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selfp.serdes.i = 0b11111110 # rising edge at fine_ts = 1
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yield
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selfp.serdes.i = 0b11111111
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yield
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self.check_input(selfp, stb=1, fine_ts=1)
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selfp.serdes.i = 0b01111111 # falling edge at fine_ts = 7
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yield
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selfp.serdes.i = 0b00000000
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yield
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self.check_input(selfp, stb=1, fine_ts=7)
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selfp.serdes.i = 0b11000000 # rising edge at fine_ts = 6
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yield
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selfp.serdes.i = 0b11111111
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yield
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self.check_input(selfp, stb=1, fine_ts=6)
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selfp.dut.rtlink.o.address = 2
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selfp.dut.rtlink.o.data = 0b11
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selfp.dut.rtlink.o.stb = 1 # set sensitivity to rising only
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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selfp.serdes.i = 0b00001111 # falling edge at fine_ts = 4
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yield
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self.check_input(selfp, stb=0) # no strobe, sensitivity is rising edge
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selfp.serdes.i = 0b11110000 # rising edge at fine_ts = 4
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yield
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self.check_input(selfp, stb=1, fine_ts=4)
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selfp.dut.rtlink.o.address = 1
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.stb = 1 # set Output Enable to 1
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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yield
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self.check_output_enable(selfp, 1)
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selfp.dut.rtlink.o.address = 0
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.fine_ts = 3
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selfp.dut.rtlink.o.stb = 1 # rising edge at fine_ts = 3
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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self.check_output(selfp, data=0b11111000)
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yield
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self.check_output(selfp, data=0xFF) # stays at 1
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selfp.dut.rtlink.o.data = 0
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selfp.dut.rtlink.o.fine_ts = 0
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selfp.dut.rtlink.o.stb = 1 # falling edge at fine_ts = 0
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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self.check_output(selfp, data=0)
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yield
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self.check_output(selfp, data=0)
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selfp.dut.rtlink.o.data = 1
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selfp.dut.rtlink.o.fine_ts = 7
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selfp.dut.rtlink.o.stb = 1 # rising edge at fine_ts = 7
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yield
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selfp.dut.rtlink.o.stb = 0
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yield
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self.check_output(selfp, data=0b10000000)
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if __name__ == "__main__":
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import sys
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from migen.sim.generic import Simulator, TopLevel
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if len(sys.argv) != 2:
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print("Incorrect command line")
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sys.exit(1)
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cls = {
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"output": _OutputTB,
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"inout": _InOutTB
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}[sys.argv[1]]
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with Simulator(cls(), TopLevel("top.vcd", clk_period=int(1/0.125))) as s:
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s.run()
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125
artiq/gateware/test/rtio/test_ttl_serdes.py
Normal file
125
artiq/gateware/test/rtio/test_ttl_serdes.py
Normal file
@ -0,0 +1,125 @@
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import unittest
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from migen import *
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from artiq.gateware.rtio.phy.ttl_serdes_generic import *
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class _FakeSerdes:
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def __init__(self):
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self.o = Signal(8)
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self.i = Signal(8)
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self.oe = Signal()
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class _TB(Module):
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def __init__(self):
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self.serdes = _FakeSerdes()
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self.submodules.dut = ClockDomainsRenamer({"rio_phy": "sys", "rio": "sys"})(
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InOut(self.serdes))
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class TestTTLSerdes(unittest.TestCase):
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def test_input(self):
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tb = _TB()
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def gen():
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yield tb.dut.rtlink.o.address.eq(2)
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yield tb.dut.rtlink.o.data.eq(0b11)
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yield tb.dut.rtlink.o.stb.eq(1) # set sensitivity to rising + falling
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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self.assertEqual((yield tb.serdes.oe), 0)
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self.assertEqual((yield tb.dut.rtlink.i.stb), 0)
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yield tb.serdes.i.eq(0b11111110) # rising edge at fine_ts = 1
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yield
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yield tb.serdes.i.eq(0b11111111)
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yield
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self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
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self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 1)
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yield tb.serdes.i.eq(0b01111111) # falling edge at fine_ts = 7
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yield
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yield tb.serdes.i.eq(0b00000000)
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yield
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self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
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self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 7)
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yield tb.serdes.i.eq(0b11000000) # rising edge at fine_ts = 6
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yield
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yield tb.serdes.i.eq(0b11111111)
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yield
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self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
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self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 6)
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yield tb.dut.rtlink.o.address.eq(2)
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yield tb.dut.rtlink.o.data.eq(0b01)
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yield tb.dut.rtlink.o.stb.eq(1) # set sensitivity to rising only
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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yield tb.serdes.i.eq(0b00001111) # falling edge at fine_ts = 4
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yield
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yield tb.serdes.i.eq(0b00000000)
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yield
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# no strobe, sensitivity is rising edge
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self.assertEqual((yield tb.dut.rtlink.i.stb), 0)
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yield tb.serdes.i.eq(0b11110000) # rising edge at fine_ts = 4
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yield
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yield tb.serdes.i.eq(0b11111111)
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yield
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self.assertEqual((yield tb.dut.rtlink.i.stb), 1)
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self.assertEqual((yield tb.dut.rtlink.i.fine_ts), 4)
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run_simulation(tb, gen())
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def test_output(self):
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tb = _TB()
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def gen():
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yield tb.dut.rtlink.o.address.eq(1)
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yield tb.dut.rtlink.o.data.eq(1)
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yield tb.dut.rtlink.o.stb.eq(1) # set Output Enable to 1
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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yield
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self.assertEqual((yield tb.serdes.oe), 1)
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yield tb.dut.rtlink.o.address.eq(0)
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yield tb.dut.rtlink.o.data.eq(1)
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yield tb.dut.rtlink.o.fine_ts.eq(3)
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yield tb.dut.rtlink.o.stb.eq(1) # rising edge at fine_ts = 3
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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self.assertEqual((yield tb.serdes.o), 0b11111000)
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yield
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self.assertEqual((yield tb.serdes.o), 0b11111111) # stays at 1
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yield tb.dut.rtlink.o.data.eq(0)
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yield tb.dut.rtlink.o.fine_ts.eq(0)
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yield tb.dut.rtlink.o.stb.eq(1) # falling edge at fine_ts = 0
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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self.assertEqual((yield tb.serdes.o), 0b00000000)
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yield
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self.assertEqual((yield tb.serdes.o), 0b00000000)
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yield tb.dut.rtlink.o.data.eq(1)
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yield tb.dut.rtlink.o.fine_ts.eq(7)
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yield tb.dut.rtlink.o.stb.eq(1) # rising edge at fine_ts = 7
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yield
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yield tb.dut.rtlink.o.stb.eq(0)
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yield
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self.assertEqual((yield tb.serdes.o), 0b10000000)
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run_simulation(tb, gen())
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