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Merge branch 'master' of github.com:m-labs/artiq

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This commit is contained in:
Sebastien Bourdeauducq 2015-08-28 10:00:16 +08:00
commit c7d9bb7edd
5 changed files with 18 additions and 6 deletions
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8
artiq/frontend/artiq_flash.sh
View File

@ -123,9 +123,13 @@ then
PROXY=bscan_spi_kc705.bit PROXY=bscan_spi_kc705.bit
BIOS_ADDR=0xaf0000 BIOS_ADDR=0xaf0000
RUNTIME_ADDR=0xb00000 RUNTIME_ADDR=0xb00000
RUNTIME_FILE=${MEZZANINE_BOARD}/runtime.fbi RUNTIME_FILE=runtime.fbi
FS_ADDR=0xb40000 FS_ADDR=0xb40000
if [ -z "$BIN_PREFIX" ]; then BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705; fi if [ -z "$BIN_PREFIX" ]
then
RUNTIME_FILE=${MEZZANINE_BOARD}/runtime.fbi
BIN_PREFIX=$ARTIQ_PREFIX/binaries/kc705
fi
search_for_proxy $PROXY search_for_proxy $PROXY
elif [ "$BOARD" == "pipistrello" ] elif [ "$BOARD" == "pipistrello" ]
then then

4
artiq/test/scheduler.py
View File

@ -1,6 +1,7 @@
import unittest import unittest
import asyncio import asyncio
import sys import sys
import os
from time import time, sleep from time import time, sleep
from artiq import * from artiq import *
@ -63,6 +64,9 @@ _handlers = {
class SchedulerCase(unittest.TestCase): class SchedulerCase(unittest.TestCase):
def setUp(self): def setUp(self):
if os.name == "nt":
self.loop = asyncio.ProactorEventLoop()
else:
self.loop = asyncio.new_event_loop() self.loop = asyncio.new_event_loop()
asyncio.set_event_loop(self.loop) asyncio.set_event_loop(self.loop)

4
artiq/test/worker.py
View File

@ -1,6 +1,7 @@
import unittest import unittest
import asyncio import asyncio
import sys import sys
import os
from time import sleep from time import sleep
from artiq import * from artiq import *
@ -59,6 +60,9 @@ def _run_experiment(class_name):
class WatchdogCase(unittest.TestCase): class WatchdogCase(unittest.TestCase):
def setUp(self): def setUp(self):
if os.name == "nt":
self.loop = asyncio.ProactorEventLoop()
else:
self.loop = asyncio.new_event_loop() self.loop = asyncio.new_event_loop()
asyncio.set_event_loop(self.loop) asyncio.set_event_loop(self.loop)

2
conda/artiq/build.sh
View File

@ -42,7 +42,7 @@ cd $SRC_DIR/misoc; $PYTHON make.py -X ../soc -t artiq_pipistrello $MISOC_EXTRA_I
cp soc/runtime/runtime.fbi $BIN_PREFIX/pipistrello/ cp soc/runtime/runtime.fbi $BIN_PREFIX/pipistrello/
cp $SRC_DIR/misoc/software/bios/bios.bin $BIN_PREFIX/pipistrello/ cp $SRC_DIR/misoc/software/bios/bios.bin $BIN_PREFIX/pipistrello/
cp $SRC_DIR/misoc/build/artiq_pipistrello-nist_qc1-pipistrello.bit $BIN_PREFIX/pipistrello/ cp $SRC_DIR/misoc/build/artiq_pipistrello-nist_qc1-pipistrello.bit $BIN_PREFIX/pipistrello/
wget http://www.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit wget https://people.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit
mv bscan_spi_lx45_csg324.bit $BIN_PREFIX/pipistrello/ mv bscan_spi_lx45_csg324.bit $BIN_PREFIX/pipistrello/
# build for KC705 NIST_QC2 # build for KC705 NIST_QC2

2
doc/manual/installing.rst
View File

@ -176,7 +176,7 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
:: ::
$ cd ~/artiq-dev $ cd ~/artiq-dev
$ wget http://www.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit $ wget https://people.phys.ethz.ch/~robertjo/bscan_spi_lx45_csg324.bit
Then copy ``~/artiq-dev/bscan_spi_lx45_csg324.bit`` to ``~/.migen``, ``/usr/local/share/migen`` or ``/usr/share/migen``. Then copy ``~/artiq-dev/bscan_spi_lx45_csg324.bit`` to ``~/.migen``, ``/usr/local/share/migen`` or ``/usr/share/migen``.