forked from M-Labs/artiq
kasli: fix disable_si5324_ibuf no_retiming
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@ -384,7 +384,7 @@ class Master(MiniSoC, AMPSoC):
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# The GTP acts up if you send any glitch to its
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# clock input, even while the PLL is held in reset.
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self.disable_si5324_ibuf = Signal(reset=1)
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self.disable_si5324_ibuf.attr.add("keep")
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self.disable_si5324_ibuf.attr.add("no_retiming")
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si5324_clkout = self.platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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@ -440,7 +440,7 @@ class Satellite(BaseSoC):
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self.csr_devices.append("rtio_moninj")
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disable_si5324_ibuf = Signal(reset=1)
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disable_si5324_ibuf.attr.add("keep")
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disable_si5324_ibuf.attr.add("no_retiming")
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si5324_clkout = platform.request("si5324_clkout")
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si5324_clkout_buf = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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