forked from M-Labs/artiq
Bootloader: Remove kusddrphy support for SDRAM
- Delete all the kusddrphy cfg flags and related code
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cb547c8a46
commit
c206e92f29
@ -8,9 +8,6 @@ mod ddr {
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DFII_COMMAND_WRDATA, DFII_COMMAND_RDDATA};
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use sdram_phy::{DFII_NPHASES, DFII_PIX_DATA_SIZE, DFII_PIX_WRDATA_ADDR, DFII_PIX_RDDATA_ADDR};
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#[cfg(kusddrphy)]
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const DDRPHY_MAX_DELAY: u16 = 512;
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#[cfg(not(kusddrphy))]
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const DDRPHY_MAX_DELAY: u16 = 32;
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const DQS_SIGNAL_COUNT: usize = DFII_PIX_DATA_SIZE / 2;
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@ -35,17 +32,12 @@ mod ddr {
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#[cfg(ddrphy_wlevel)]
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unsafe fn write_level_scan(logger: &mut Option<&mut dyn fmt::Write>) {
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#[cfg(kusddrphy)]
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log!(logger, "DQS initial delay: {} taps\n", ddrphy::wdly_dqs_taps_read());
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log!(logger, "Write leveling scan:\n");
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enable_write_leveling(true);
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spin_cycles(100);
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#[cfg(not(kusddrphy))]
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let ddrphy_max_delay : u16 = DDRPHY_MAX_DELAY;
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#[cfg(kusddrphy)]
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let ddrphy_max_delay : u16 = DDRPHY_MAX_DELAY - ddrphy::wdly_dqs_taps_read();
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for n in 0..DQS_SIGNAL_COUNT {
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let dq_addr = dfii::PI0_RDDATA_ADDR
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@ -57,10 +49,6 @@ mod ddr {
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ddrphy::wdly_dq_rst_write(1);
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ddrphy::wdly_dqs_rst_write(1);
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#[cfg(kusddrphy)]
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for _ in 0..ddrphy::wdly_dqs_taps_read() {
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ddrphy::wdly_dqs_inc_write(1);
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}
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let mut dq;
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for _ in 0..ddrphy_max_delay {
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@ -88,17 +76,12 @@ mod ddr {
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unsafe fn write_level(logger: &mut Option<&mut dyn fmt::Write>,
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delay: &mut [u16; DQS_SIGNAL_COUNT],
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high_skew: &mut [bool; DQS_SIGNAL_COUNT]) -> bool {
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#[cfg(kusddrphy)]
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log!(logger, "DQS initial delay: {} taps\n", ddrphy::wdly_dqs_taps_read());
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log!(logger, "Write leveling: ");
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enable_write_leveling(true);
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spin_cycles(100);
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#[cfg(not(kusddrphy))]
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let ddrphy_max_delay : u16 = DDRPHY_MAX_DELAY;
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#[cfg(kusddrphy)]
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let ddrphy_max_delay : u16 = DDRPHY_MAX_DELAY - ddrphy::wdly_dqs_taps_read();
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let mut failed = false;
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for n in 0..DQS_SIGNAL_COUNT {
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@ -112,10 +95,6 @@ mod ddr {
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ddrphy::wdly_dq_rst_write(1);
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ddrphy::wdly_dqs_rst_write(1);
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#[cfg(kusddrphy)]
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for _ in 0..ddrphy::wdly_dqs_taps_read() {
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ddrphy::wdly_dqs_inc_write(1);
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}
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ddrphy::wlevel_strobe_write(1);
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spin_cycles(10);
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@ -146,11 +125,6 @@ mod ddr {
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dq = ptr::read_volatile(dq_addr);
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}
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// Get a bit further into the 0 zone
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#[cfg(kusddrphy)]
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for _ in 0..32 {
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incr_delay();
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}
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}
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while dq == 0 {
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@ -191,9 +165,6 @@ mod ddr {
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if delay[n] > threshold {
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ddrphy::dly_sel_write(1 << n);
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#[cfg(kusddrphy)]
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ddrphy::rdly_dq_bitslip_write(1);
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#[cfg(not(kusddrphy))]
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for _ in 0..3 {
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ddrphy::rdly_dq_bitslip_write(1);
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}
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@ -451,13 +422,9 @@ pub unsafe fn init(mut _logger: Option<&mut dyn fmt::Write>) -> bool {
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#[cfg(has_ddrphy)]
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{
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#[cfg(kusddrphy)]
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csr::ddrphy::en_vtc_write(0);
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if !ddr::level(&mut _logger) {
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return false
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}
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#[cfg(kusddrphy)]
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csr::ddrphy::en_vtc_write(1);
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}
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csr::dfii::control_write(sdram_phy::DFII_CONTROL_SEL);
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