forked from M-Labs/artiq
ad9910: port to NAC3
This commit is contained in:
parent
0256c91d53
commit
be07481eb5
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@ -1,15 +1,35 @@
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from numpy import int32, int64
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from artiq.language.core import kernel, portable
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from artiq.language.core import *
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from artiq.language.units import us, ms
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice import urukul
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from artiq.coredevice.urukul import DEFAULT_PROFILE
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from artiq.coredevice.spi2 import *
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from artiq.coredevice.urukul import *
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from artiq.coredevice.urukul import *
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from artiq.coredevice.ttl import TTLOut
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from artiq.coredevice.kasli_i2c import KasliEEPROM # NAC3TODO
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# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/189
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@nac3
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class ValueError(Exception):
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pass
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# NAC3TODO work around https://git.m-labs.hk/M-Labs/nac3/issues/206
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@portable
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def min(a: int32, b: int32) -> int32:
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if a > b:
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return b
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else:
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return a
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@portable
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def max(a: int32, b: int32) -> int32:
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if a > b:
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return a
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else:
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return b
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# Work around ARTIQ-Python import machinery
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urukul_sta_pll_lock = urukul.urukul_sta_pll_lock
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urukul_sta_smp_err = urukul.urukul_sta_smp_err
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__all__ = [
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"AD9910",
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@ -62,8 +82,12 @@ RAM_MODE_CONT_RAMPUP = 4
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# Default profile for RAM mode
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_DEFAULT_PROFILE_RAM = 0
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@nac3
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class SyncDataUser:
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core: KernelInvariant[Core]
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sync_delay_seed: Kernel[int32]
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io_update_delay: Kernel[int32]
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def __init__(self, core, sync_delay_seed, io_update_delay):
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self.core = core
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self.sync_delay_seed = sync_delay_seed
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@ -74,7 +98,14 @@ class SyncDataUser:
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pass
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@nac3
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class SyncDataEeprom:
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core: KernelInvariant[Core]
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eeprom_device: KernelInvariant[KasliEEPROM] # NAC3TODO support generic EEPROM driver
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eeprom_offset: KernelInvariant[int32]
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sync_delay_seed: Kernel[int32]
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io_update_delay: Kernel[int32]
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def __init__(self, dmgr, core, eeprom_str):
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self.core = core
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@ -100,6 +131,7 @@ class SyncDataEeprom:
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self.io_update_delay = int32(io_update_delay)
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@nac3
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class AD9910:
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"""
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AD9910 DDS channel on Urukul.
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@ -136,9 +168,24 @@ class AD9910:
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to the same string value.
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"""
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core: KernelInvariant[Core]
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cpld: KernelInvariant[CPLD]
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bus: KernelInvariant[SPIMaster]
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chip_select: KernelInvariant[int32]
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pll_en: KernelInvariant[bool]
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pll_n: KernelInvariant[int32]
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pll_vco: KernelInvariant[int32]
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pll_cp: KernelInvariant[int32]
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ftw_per_hz: KernelInvariant[float]
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sysclk_per_mu: KernelInvariant[int32]
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sysclk: KernelInvariant[float]
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sw: KernelInvariant[TTLOut]
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sync_data: KernelInvariant[SyncDataUser]
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phase_mode: Kernel[int32]
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=40, pll_cp=7, pll_vco=5, sync_delay_seed=-1,
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io_update_delay=0, pll_en=1):
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io_update_delay=0, pll_en=True):
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self.kernel_invariants = {"cpld", "core", "bus", "chip_select",
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"pll_en", "pll_n", "pll_vco", "pll_cp",
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"ftw_per_hz", "sysclk_per_mu", "sysclk",
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@ -150,7 +197,7 @@ class AD9910:
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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self.kernel_invariants.add("sw")
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# NAC3TODO: support no sw
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clk = self.cpld.refclk / [4, 1, 2, 4][self.cpld.clk_div]
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self.pll_en = pll_en
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self.pll_n = pll_n
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@ -172,6 +219,7 @@ class AD9910:
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self.sysclk_per_mu = int(round(sysclk * self.core.ref_period))
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self.sysclk = sysclk
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# NAC3TODO
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if isinstance(sync_delay_seed, str) or isinstance(io_update_delay,
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str):
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if sync_delay_seed != io_update_delay:
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@ -236,8 +284,8 @@ class AD9910:
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:param addr: Register address
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:param data: Data to be written
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 24,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 24,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr << 24) | ((data & 0xffff) << 8))
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@kernel
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@ -247,11 +295,11 @@ class AD9910:
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:param addr: Register address
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:param data: Data to be written
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG, 8,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write(addr << 24)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 32,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write(data)
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@kernel
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@ -260,12 +308,12 @@ class AD9910:
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:param addr: Register address
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG, 8,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | 0x80) << 24)
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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16, urukul.SPIT_DDS_RD, self.chip_select)
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SPI_CONFIG | SPI_END | SPI_INPUT,
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16, SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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return self.bus.read()
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@ -275,12 +323,12 @@ class AD9910:
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:param addr: Register address
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG, 8,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | 0x80) << 24)
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, urukul.SPIT_DDS_RD, self.chip_select)
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SPI_CONFIG | SPI_END | SPI_INPUT,
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32, SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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return self.bus.read()
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@ -292,20 +340,20 @@ class AD9910:
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:return: 64 bit integer register value
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"""
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self.bus.set_config_mu(
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urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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SPI_CONFIG, 8,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write((addr | 0x80) << 24)
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_INPUT, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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SPI_CONFIG | SPI_INPUT, 32,
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SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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SPI_CONFIG | SPI_END | SPI_INPUT, 32,
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SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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hi = self.bus.read()
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lo = self.bus.read()
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return (int64(hi) << 32) | lo
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return (int64(hi) << int64(32)) | int64(lo)
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@kernel
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def write64(self, addr: int32, data_high: int32, data_low: int32):
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@ -315,14 +363,14 @@ class AD9910:
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:param data_high: High (MSB) 32 bits of the data
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:param data_low: Low (LSB) 32 data bits
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG, 8,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write(addr << 24)
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self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG, 32,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write(data_high)
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 32,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write(data_low)
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@kernel
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@ -335,15 +383,15 @@ class AD9910:
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:param data: Data to be written to RAM.
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
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self.bus.set_config_mu(SPI_CONFIG, 8, SPIT_DDS_WR,
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self.chip_select)
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self.bus.write(_AD9910_REG_RAM << 24)
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self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG, 32,
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SPIT_DDS_WR, self.chip_select)
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for i in range(len(data) - 1):
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self.bus.write(data[i])
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
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urukul.SPIT_DDS_WR, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG | SPI_END, 32,
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SPIT_DDS_WR, self.chip_select)
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self.bus.write(data[len(data) - 1])
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@kernel
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@ -356,21 +404,21 @@ class AD9910:
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:param data: List to be filled with data read from RAM.
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"""
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self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
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self.bus.set_config_mu(SPI_CONFIG, 8, SPIT_DDS_WR,
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self.chip_select)
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self.bus.write((_AD9910_REG_RAM | 0x80) << 24)
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n = len(data) - 1
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if n > 0:
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self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_INPUT, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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self.bus.set_config_mu(SPI_CONFIG | SPI_INPUT, 32,
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SPIT_DDS_RD, self.chip_select)
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preload = min(n, 8)
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for i in range(n):
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self.bus.write(0)
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if i >= preload:
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data[i - preload] = self.bus.read()
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self.bus.set_config_mu(
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urukul.SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END, 32,
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urukul.SPIT_DDS_RD, self.chip_select)
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SPI_CONFIG | SPI_INPUT | SPI_END, 32,
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SPIT_DDS_RD, self.chip_select)
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self.bus.write(0)
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for i in range(preload + 1):
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data[(n - preload) + i] = self.bus.read()
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@ -463,50 +511,50 @@ class AD9910:
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if self.sync_data.sync_delay_seed >= 0 and not self.cpld.sync_div:
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raise ValueError("parent cpld does not drive SYNC")
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if self.sync_data.sync_delay_seed >= 0:
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if self.sysclk_per_mu != self.sysclk * self.core.ref_period:
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if float(self.sysclk_per_mu) != self.sysclk * self.core.ref_period:
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raise ValueError("incorrect clock ratio for synchronization")
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delay(50 * ms) # slack
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self.core.delay(50. * ms) # slack
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# Set SPI mode
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self.set_cfr1()
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self.cpld.io_update.pulse(1 * us)
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delay(1 * ms)
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self.cpld.io_update.pulse(1. * us)
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self.core.delay(1. * ms)
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if not blind:
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# Use the AUX DAC setting to identify and confirm presence
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aux_dac = self.read32(_AD9910_REG_AUX_DAC)
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if aux_dac & 0xff != 0x7f:
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raise ValueError("Urukul AD9910 AUX_DAC mismatch")
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delay(50 * us) # slack
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self.core.delay(50. * us) # slack
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# Configure PLL settings and bring up PLL
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# enable amplitude scale from profiles
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# read effective FTW
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# sync timing validation disable (enabled later)
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self.set_cfr2(sync_validation_disable=1)
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self.cpld.io_update.pulse(1 * us)
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self.cpld.io_update.pulse(1. * us)
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cfr3 = (0x0807c000 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_en << 8) |
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(self.pll_n << 1))
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(self.pll_cp << 19) | (int32(self.pll_en) << 8) |
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(int32(self.pll_n) << 1))
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self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset
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self.cpld.io_update.pulse(1 * us)
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self.cpld.io_update.pulse(1. * us)
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if self.pll_en:
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self.write32(_AD9910_REG_CFR3, cfr3)
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self.cpld.io_update.pulse(1 * us)
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self.cpld.io_update.pulse(1. * us)
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if blind:
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delay(100 * ms)
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self.core.delay(100. * ms)
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else:
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# Wait for PLL lock, up to 100 ms
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for i in range(100):
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sta = self.cpld.sta_read()
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lock = urukul_sta_pll_lock(sta)
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delay(1 * ms)
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if lock & (1 << self.chip_select - 4):
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self.core.delay(1. * ms)
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if lock & (1 << self.chip_select - 4) != 0:
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break
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if i >= 100 - 1:
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raise ValueError("PLL lock timeout")
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delay(10 * us) # slack
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self.core.delay(10. * us) # slack
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if self.sync_data.sync_delay_seed >= 0 and not blind:
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self.tune_sync_delay(self.sync_data.sync_delay_seed)
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delay(1 * ms)
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self.core.delay(1. * ms)
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@kernel
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def power_down(self, bits: int32 = 0b1111):
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@ -515,7 +563,7 @@ class AD9910:
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:param bits: Power down bits, see datasheet
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"""
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self.set_cfr1(power_down=bits)
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self.cpld.io_update.pulse(1 * us)
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self.cpld.io_update.pulse(1. * us)
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@kernel
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def set_mu(self, ftw: int32 = 0, pow_: int32 = 0, asf: int32 = 0x3fff,
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@ -557,15 +605,15 @@ class AD9910:
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phase_mode = self.phase_mode
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# Align to coarse RTIO which aligns SYNC_CLK. I.e. clear fine TSC
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# This will not cause a collision or sequence error.
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at_mu(now_mu() & ~7)
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at_mu(now_mu() & int64(~7))
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if phase_mode != PHASE_MODE_CONTINUOUS:
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# Auto-clear phase accumulator on IO_UPDATE.
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# This is active already for the next IO_UPDATE
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self.set_cfr1(phase_autoclear=1)
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if phase_mode == PHASE_MODE_TRACKING and ref_time_mu < 0:
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if phase_mode == PHASE_MODE_TRACKING and ref_time_mu < int64(0):
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# set default fiducial time stamp
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ref_time_mu = 0
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if ref_time_mu >= 0:
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ref_time_mu = int64(0)
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if ref_time_mu >= int64(0):
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# 32 LSB are sufficient.
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# Also no need to use IO_UPDATE time as this
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# is equivalent to an output pipeline latency.
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@ -583,8 +631,8 @@ class AD9910:
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if not ram_destination == RAM_DEST_POW:
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self.set_pow(pow_)
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delay_mu(int64(self.sync_data.io_update_delay))
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self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYN_CCLK
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at_mu(now_mu() & ~7) # clear fine TSC again
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self.cpld.io_update.pulse_mu(int64(8)) # assumes 8 mu > t_SYN_CCLK
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at_mu(now_mu() & int64(~7)) # clear fine TSC again
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if phase_mode != PHASE_MODE_CONTINUOUS:
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self.set_cfr1()
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# future IO_UPDATE will activate
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@ -606,8 +654,8 @@ class AD9910:
|
|||
data = int64(self.read64(_AD9910_REG_PROFILE0 + profile))
|
||||
# Extract and return fields
|
||||
ftw = int32(data)
|
||||
pow_ = int32((data >> 32) & 0xffff)
|
||||
asf = int32((data >> 48) & 0x3fff)
|
||||
pow_ = int32(data >> int64(32)) & 0xffff
|
||||
asf = int32(data >> int64(48)) & 0x3fff
|
||||
return ftw, pow_, asf
|
||||
|
||||
@kernel
|
||||
|
|
@ -703,13 +751,13 @@ class AD9910:
|
|||
"""Return the frequency corresponding to the given frequency tuning
|
||||
word.
|
||||
"""
|
||||
return ftw / self.ftw_per_hz
|
||||
return float(ftw) / self.ftw_per_hz
|
||||
|
||||
@portable
|
||||
def turns_to_pow(self, turns: float) -> int32:
|
||||
"""Return the 16-bit phase offset word corresponding to the given phase
|
||||
in turns."""
|
||||
return int32(round(turns * 0x10000)) & int32(0xffff)
|
||||
return round(turns * float(0x10000)) & 0xffff
|
||||
|
||||
@portable
|
||||
def pow_to_turns(self, pow_: int32) -> float:
|
||||
|
|
@ -721,7 +769,7 @@ class AD9910:
|
|||
def amplitude_to_asf(self, amplitude: float) -> int32:
|
||||
"""Return 14-bit amplitude scale factor corresponding to given
|
||||
fractional amplitude."""
|
||||
code = int32(round(amplitude * 0x3fff))
|
||||
code = round(amplitude * float(0x3fff))
|
||||
if code < 0 or code > 0x3fff:
|
||||
raise ValueError("Invalid AD9910 fractional amplitude!")
|
||||
return code
|
||||
|
|
@ -730,7 +778,7 @@ class AD9910:
|
|||
def asf_to_amplitude(self, asf: int32) -> float:
|
||||
"""Return amplitude as a fraction of full scale corresponding to given
|
||||
amplitude scale factor."""
|
||||
return asf / float(0x3fff)
|
||||
return float(asf) / float(0x3fff)
|
||||
|
||||
@portable
|
||||
def frequency_to_ram(self, frequency: list[float], ram: list[int32]):
|
||||
|
|
@ -972,10 +1020,10 @@ class AD9910:
|
|||
Also modifies CFR2.
|
||||
"""
|
||||
self.set_cfr2(sync_validation_disable=1) # clear SMP_ERR
|
||||
self.cpld.io_update.pulse(1 * us)
|
||||
delay(10 * us) # slack
|
||||
self.cpld.io_update.pulse(1. * us)
|
||||
self.core.delay(10. * us) # slack
|
||||
self.set_cfr2(sync_validation_disable=0) # enable SMP_ERR
|
||||
self.cpld.io_update.pulse(1 * us)
|
||||
self.cpld.io_update.pulse(1. * us)
|
||||
|
||||
@kernel
|
||||
def tune_sync_delay(self,
|
||||
|
|
@ -1006,7 +1054,7 @@ class AD9910:
|
|||
next_seed = -1
|
||||
for in_delay in range(search_span - 2 * window):
|
||||
# alternate search direction around search_seed
|
||||
if in_delay & 1:
|
||||
if in_delay & 1 != 0:
|
||||
in_delay = -in_delay
|
||||
in_delay = search_seed + (in_delay >> 1)
|
||||
if in_delay < 0 or in_delay > 31:
|
||||
|
|
@ -1014,9 +1062,9 @@ class AD9910:
|
|||
self.set_sync(in_delay, window)
|
||||
self.clear_smp_err()
|
||||
# integrate SMP_ERR statistics for a few hundred cycles
|
||||
delay(100 * us)
|
||||
self.core.delay(100. * us)
|
||||
err = urukul_sta_smp_err(self.cpld.sta_read())
|
||||
delay(100 * us) # slack
|
||||
self.core.delay(100. * us) # slack
|
||||
if not (err >> (self.chip_select - 4)) & 1:
|
||||
next_seed = in_delay
|
||||
break
|
||||
|
|
@ -1028,7 +1076,7 @@ class AD9910:
|
|||
window = max(min_window, window - 1 - margin)
|
||||
self.set_sync(search_seed, window)
|
||||
self.clear_smp_err()
|
||||
delay(100 * us) # slack
|
||||
self.core.delay(100. * us) # slack
|
||||
return search_seed, window
|
||||
else:
|
||||
break
|
||||
|
|
@ -1060,21 +1108,21 @@ class AD9910:
|
|||
# dFTW = 1, (work around negative slope)
|
||||
self.write64(_AD9910_REG_RAMP_STEP, -1, 0)
|
||||
# delay io_update after RTIO edge
|
||||
t = now_mu() + 8 & ~7
|
||||
t = now_mu() + int64(8) & int64(~7)
|
||||
at_mu(t + delay_start)
|
||||
# assumes a maximum t_SYNC_CLK period
|
||||
self.cpld.io_update.pulse_mu(16 - delay_start) # realign
|
||||
self.cpld.io_update.pulse_mu(int64(16) - delay_start) # realign
|
||||
# disable DRG autoclear and LRR on io_update
|
||||
self.set_cfr1()
|
||||
# stop DRG
|
||||
self.write64(_AD9910_REG_RAMP_STEP, 0, 0)
|
||||
at_mu(t + 0x1000 + delay_stop)
|
||||
self.cpld.io_update.pulse_mu(16 - delay_stop) # realign
|
||||
at_mu(t + int64(0x1000) + delay_stop)
|
||||
self.cpld.io_update.pulse_mu(int64(16) - delay_stop) # realign
|
||||
ftw = self.read32(_AD9910_REG_FTW) # read out effective FTW
|
||||
delay(100 * us) # slack
|
||||
self.core.delay(100. * us) # slack
|
||||
# disable DRG
|
||||
self.set_cfr2(drg_enable=0)
|
||||
self.cpld.io_update.pulse_mu(8)
|
||||
self.cpld.io_update.pulse_mu(int64(8))
|
||||
return ftw & 1
|
||||
|
||||
@kernel
|
||||
|
|
@ -1100,14 +1148,14 @@ class AD9910:
|
|||
t = 0
|
||||
# check whether the sync edge is strictly between i, i+2
|
||||
for j in range(repeat):
|
||||
t += self.measure_io_update_alignment(i, i + 2)
|
||||
t += self.measure_io_update_alignment(int64(i), int64(i + 2))
|
||||
if t != 0: # no certain edge
|
||||
continue
|
||||
# check left/right half: i,i+1 and i+1,i+2
|
||||
t1 = [0, 0]
|
||||
for j in range(repeat):
|
||||
t1[0] += self.measure_io_update_alignment(i, i + 1)
|
||||
t1[1] += self.measure_io_update_alignment(i + 1, i + 2)
|
||||
t1[0] += self.measure_io_update_alignment(int64(i), int64(i + 1))
|
||||
t1[1] += self.measure_io_update_alignment(int64(i + 1), int64(i + 2))
|
||||
if ((t1[0] == 0 and t1[1] == 0) or
|
||||
(t1[0] == repeat and t1[1] == repeat)):
|
||||
# edge is not close to i + 1, can't interpret result
|
||||
|
|
|
|||
|
|
@ -22,28 +22,34 @@
|
|||
"ports": [2, 3],
|
||||
"clk_sel": 2
|
||||
},
|
||||
{
|
||||
"type": "urukul",
|
||||
"dds": "ad9910",
|
||||
"ports": [4, 5],
|
||||
"clk_sel": 2
|
||||
},
|
||||
{
|
||||
"type": "sampler",
|
||||
"ports": [4]
|
||||
"ports": [6]
|
||||
},
|
||||
{
|
||||
"type": "dio",
|
||||
"ports": [5],
|
||||
"ports": [7],
|
||||
"bank_direction_low": "input",
|
||||
"bank_direction_high": "output",
|
||||
"edge_counter": true
|
||||
},
|
||||
{
|
||||
"type": "grabber",
|
||||
"ports": [6]
|
||||
"ports": [8]
|
||||
},
|
||||
{
|
||||
"type": "fastino",
|
||||
"ports": [7]
|
||||
"ports": [9]
|
||||
},
|
||||
{
|
||||
"type": "phaser",
|
||||
"ports": [8]
|
||||
"ports": [10]
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ from artiq.coredevice.mirny import Mirny as MirnyCPLD
|
|||
from artiq.coredevice.adf5356 import ADF5356
|
||||
from artiq.coredevice.urukul import CPLD as UrukulCPLD
|
||||
from artiq.coredevice.ad9912 import AD9912
|
||||
from artiq.coredevice.ad9910 import AD9910
|
||||
from artiq.coredevice.sampler import Sampler
|
||||
from artiq.coredevice.edge_counter import EdgeCounter
|
||||
from artiq.coredevice.grabber import Grabber
|
||||
|
|
@ -24,6 +25,8 @@ class NAC3Devices(EnvExperiment):
|
|||
urukul0_cpld: KernelInvariant[UrukulCPLD]
|
||||
eeprom_urukul0: KernelInvariant[KasliEEPROM]
|
||||
urukul0_ch0: KernelInvariant[AD9912]
|
||||
urukul1_cpld: KernelInvariant[UrukulCPLD]
|
||||
urukul1_ch0: KernelInvariant[AD9910]
|
||||
sampler0: KernelInvariant[Sampler]
|
||||
ttl0_counter: KernelInvariant[EdgeCounter]
|
||||
grabber0: KernelInvariant[Grabber]
|
||||
|
|
@ -39,6 +42,8 @@ class NAC3Devices(EnvExperiment):
|
|||
self.setattr_device("urukul0_cpld")
|
||||
self.setattr_device("eeprom_urukul0")
|
||||
self.setattr_device("urukul0_ch0")
|
||||
self.setattr_device("urukul1_cpld")
|
||||
self.setattr_device("urukul1_ch0")
|
||||
self.setattr_device("sampler0")
|
||||
self.setattr_device("ttl0_counter")
|
||||
self.setattr_device("grabber0")
|
||||
|
|
|
|||
Loading…
Reference in New Issue