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novogorny: fix gain register length

This commit is contained in:
Robert Jördens 2018-02-22 18:45:55 +00:00
parent 1452cd7447
commit bc5e949bb4
1 changed files with 1 additions and 1 deletions
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2
artiq/coredevice/novogorny.py
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@ -100,7 +100,7 @@ class Novogorny:
self.gains &= ~(0b11 << (channel*2))
self.gains |= gain << (channel*2)
self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END,
2, self.div, SPI_CS_SR)
16, self.div, SPI_CS_SR)
self.bus.write(self.gains << 16)
@kernel