novogorny: fix gain register length

2018-02-22 18:45:55 +00:00 · 2018-02-22 18:45:55 +00:00 · bc5e949bb4
commit bc5e949bb4
parent 1452cd7447
1 changed files with 1 additions and 1 deletions
--- a/artiq/coredevice/novogorny.py
+++ b/artiq/coredevice/novogorny.py
@ -100,7 +100,7 @@ class Novogorny:
        self.gains &= ~(0b11 << (channel*2))
        self.gains |= gain << (channel*2)
        self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END,
-                               2, self.div, SPI_CS_SR)
+                               16, self.div, SPI_CS_SR)
        self.bus.write(self.gains << 16)

    @kernel