forked from M-Labs/artiq
phaser: fix comment
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@ -21,7 +21,7 @@ jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_checksum = jesd_settings.get_configuration_checksum()
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# external clk=2000MHz
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# pclock=250MHz
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# deviceclock_fpga=500MHz
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# deviceclock_fpga=250MHz
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# deviceclock_dac=2000MHz
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